Counters

Consider the following four-bit binary counter integrated circuit (IC). When clocked by the square wave signal generator, it counts from 0000 to 1111 in sixteen steps and then “recycles” back to 0000 again in a single step:

There are many applications, though, where we do not wish the counter circuit to count all the way up to full count (1111), but rather recycle at some lesser terminal count value. Take for instance the application of BCD counting: from 0000 to 1001 and back again. Here is one way to truncate the counting sequence of a binary counter so that it becomes a BCD counter:

Explain how the NAND gate forces this counter to recycle after an output of 1001 instead of counting all the way up to 1111. (Hint: the reset function of this IC is assumed to be asynchronous, meaning the counter output resets to 0000 immediately when the [RST] terminal goes low.)

Also, show how you would modify this circuit to do the same count sequence (BCD) assuming the IC has a synchronous reset function, meaning the counter resets to 0000 if [RST] is low and the clock input sees a pulse.

Suppose you had an astable multivibrator circuit that output a very precise 1 Hz square-wave signal, but you had an application which requires a pulse once every minute rather than once every second. Knowing that there are 60 seconds in a minute, can you think of a way to use digital counters to act as a “frequency divider” so that every 60 multivibrator pulses equates to 1 output pulse?

You don’t have a divide-by-60 counter available, but you do have several divide-by-10 (“decade”) counters at your disposal. Engineer a solution using these counter units:

Note: assume these counter ICs have asynchronous resets.

When counters are used as frequency dividers, they are often drawn as simple boxes with one input and one output each, like this:

Calculate the four output frequencies (f_out1 through f_out4) given an input frequency of 1.5 kHz:

f_out1 =

f_out2 =

f_out3 =

f_out4 =