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Category: All IP Cores (1032)

DESL Core VHDL Implementation

DESL Core VHDL Implementation

VHDL implementation of the DESL block cipher (iterative architecture).

License : GPL
Language : VHDL
DESLX Core Block Cipher in VHDL

DESLX Core Block Cipher in VHDL

VHDL implementation of the DESLX block cipher (iterative architecture).

License : GPL
Language : VHDL
DESX Block Cipher Core in VHDL Implementation

DESX Block Cipher Core in VHDL Implementation

VHDL implementation of the DESX block cipher (iterative architecture).

License : GPL
Language : VHDL
AES with Galois Counter Mode in FPGA

AES with Galois Counter Mode in FPGA

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : Others
Language : Verilog
GOST 28147-89 Core Implementation on Xilinx

GOST 28147-89 Core Implementation on Xilinx

This is a implementation of the GOST 28147-89 - a Soviet and Russian government standard symmetric key block cipher. GOST 28147-89 has a 64-bit…

License : BSD
Language : Verilog
GOST 28147-89 Block Cipher

GOST 28147-89 Block Cipher

The GOST block cipher, defined in standard GOST 28147-89, is a Soviet and Russian government standard symmetric key block cipher. Developed in the…

License : BSD
Language : Verilog
IDEA Symmetric Block Cipher using 128 bit Key

IDEA Symmetric Block Cipher using 128 bit Key

The IDEA (International Data Encryption Algorithm) is a symmetric-key block cipher that can encrypts 64-bits plaintexts to 64-bit ciphertexts using…

RSA Cryptosystem High Radix Montgomery Algorithm

RSA Cryptosystem High Radix Montgomery Algorithm

RSA Cryptosystem is widely used in information technology. It encrypts and decrypts messages using public key mechanism. The security of this…

High Throughput Low Area AES Core

High Throughput Low Area AES Core

The High Throughput Low Area AES IP core implements the Rijndael encryption & decryption algorithm used in the AES standard. The standalone…

License : LGPL
Language : Verilog
IOTA PoW Computation Pearl-Driver for FPGAs

IOTA PoW Computation Pearl-Driver for FPGAs

Overview IOTA PoW needs a lot of computational power which makes sending transactions on smaller microcontrollers (like ARM) very slow. This is a…

License : Others
Language : VHDL
Simple to Use SHA-2 Algorithm

Simple to Use SHA-2 Algorithm

Simple to use SHA-2 algorithm Is a VHDL implementation of SHA-224/256 core. Major project choice is semplicity: just feed core with message a chunk…

License : LGPL
Language : VHDL
Mini Advanced Encryption Standard - Mini AES

Mini Advanced Encryption Standard - Mini AES

Mini AES Advanced Encryption Standard (AES) implementation with small area/resources utilization. Features - Encryption and Decryption unit in…

License : BSD
Language : VHDL
MD5 Pipelined Implementations in Verilog

MD5 Pipelined Implementations in Verilog

A high throughput, 64-stage pipelined implementation of MD5 written in Verilog. Completes one hash per cycle.

License : LGPL
Language : Verilog
PRESENT - 32 bit Hardware Lightweight Block Cipher

PRESENT - 32 bit Hardware Lightweight Block Cipher

Present is a lightweight block cipher dedicated to implement in Hardware. It was developed by Knudsen team. This cipher operates on the 64 bit text…

License : LGPL
Language : VHDL
NOEKEON Core (Lightweight Block Cipher)

NOEKEON Core (Lightweight Block Cipher)

VHDL implementation of the NOEKEON block cipher (iterative architecture).

License : GPL
Language : VHDL
Nugroho Free Crypto Cores

Nugroho Free Crypto Cores

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License : BSD
Language : VHDL
GridVortex SHA256 Hash Core Algorithm

GridVortex SHA256 Hash Core Algorithm

This is the GV_SHA256, a fast SHA-256 engine (580Mbps @ 74MHz), fully compliant to the NIST FIPS-180-4 SHA-256 approved algorithm. It is…

License : LGPL
Language : VHDL
Nugroho Free Hash Cores

Nugroho Free Hash Cores

Nugroho Free Hash Cores (NFHC) currently support SHA-1, SHA-256, SHA-512 from FIPS-180 standard.

License : BSD
Language : VHDL
Pipelined Architecture of AES 128 Bit

Pipelined Architecture of AES 128 Bit

This is a fully pipelined implementation of the AES (rijndael) cipher with 128 bit keysize. Post place and route logs show the maximum speed to be…

License : LGPL
Language : VHDL
Present - Block Cipher Encryption Core

Present - Block Cipher Encryption Core

About Present Block Cipher Present is a lightweight block cipher designed for hardware constrained applications such as RFID tags and Smart Cards.…

License : LGPL
Language : Verilog