[Cereon is a registered trademark of Cybernetic Intelligence, GmbH, Switzerland. The project lead is Andrey Kapustin] The Cereon architecture…
This core is a simple and small VGA controller. It drives vga monitors with an 800x600 resolution and 72Hz vertical refresh rate (50MHz pixel…
CLAW is a two-way multithreaded (8 threads) VLIW Processor core. Simultaneous multithreading (SMT) is a technique for improving the overall…
The project is to develope LPC controller and peripherals. LPC(Low Pin Count) is designed by Intel, and described in the LPC Interface…
BRISC microprocessor is an FPGA optimized micro-sequencer based on paper "Implementation of Microprogrammed Control in FPGAs" by Bruce W.…
This is the basic datapath of DLX microprocessor that suports Simple memory access instructions (lw, sw) Arithmetic and logical instructions (add,…
Dallas one-wire protocol with a DS1821 top level demo This project was done for a senior project in the ASIC senior project sequence at Oregon…
Mobile IPv4 Network eMotion mobility protocol. Network Mobility (NEMO) is an Internet standards track protocol defined in RFC 5177. The protocol…
This is an design based on Altera's ACEX1K. This project schematics and PCBs has been designed with OrCAD 9.2. Therefore, i recommend you to…
This is an MFM floppy drive controller designed to interface to standard 3.5" 1.44MB floppy drives. This is a complete floppy controller which…
The FSL2Serial peripheral is an XPS peripheral designed to allow a processor (or other piece of hardware) to send data to a UART via an FSL bus.…
To design a large bit adder computation for high performance When we design an adder for a x bit size, for example 16 bits, a certain delay is…
JPEG Decoder is the hardware source code of Verilog which decodes the RGB data from the JPEG data. Features Base line DCT Huffman Decode Sampling…
Manchester Encoding: In manchester encoding '1' is transmitted as 0 in first half of the clock and 1 in the second half of the clock and…
This project contains a Basic and generic UART SerDes controller. Configuration: -Enable/Disable Odd/Even parity bit -bit stop number…
GCC Compiler for OCMIPS I built the GCC compiler for ocmips using the cross tool scripts written by Dan Kegel, you can download the scripts from…
MD5 Hash Core RFC 1321 Thihs core fully implements the MD5 (Message Digest Algorithm RFC 1321). The core can be used for data authentication in…
MIPS Single Cycle Microprocessor IP Core, used to determine problems with microprocessors.
Profibus Profibus DP - VHDL BUS Model The main intention of this document is to describe VHDL formal model of the Profibus DP fieldbus. Document…
Cores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into…
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