The trapezoidal shaping is a method of pulse height measurement, described in "V.Radeka,'Trapezoidal Filtering of Signals from Large…
Performance counters are very useful in performance profiling because the limitation of software profiling. Therefore they are available in most of…
This SDRAM controller is optimised for speed. It works efficiently at frequencies higher than 100 Mhz. It's been tested on Altera devices and…
In order to add a better Programmble Interrupt Controller(PIC), I read a the datasheet of Intel8259.I find some of the functions in Intel8259 may…
Synthesizable soft STS-1 framer core used in SONET at 51.84 Mbps STS-1 is the basic signal of SONET system working at 51.84 Mbps. It is able to…
SystemC CORDIC This project provides one possible implementation of CORDIC in SystemC. The CORDIC core is pipelined and has some limited power-save…
This short and simple package makes it easy to read and write wave files for signal processing in simulations. This is usefull if you want to check…
This IP implements the CAVLC parsing process in ITU-T H.264 (05/2003) Features - Compatible with ITU-T H.264 (05/2003), but it do not calculate nC…
This IP core is a configurable feedforward Artificial Neural Network (ANN). ANNs are Artificial Intelligence (AI) algorithms biologically inspired…
Cores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into…
Cores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into…
Gaussian Pseudo-random Number Generator is a fix-point entity implemented with VHDL, used for generating complex Gaussian pseudo-random numbers.…
A Complex arithmetic library for arithmetic operations is needed in many signal processing applications. This project will present a complex…
This IP core provides a resource efficient implementation of a Booth Array Multiplier for Xilinx FPGAs as proposed in: M. Kumm, S. Abbas, and P.…
This project implements a parameterized Reed Solomon decoder for use in OFDM wireless systems. Features Decodes full length (n = 255, t = 16) and…
This project shows a 4-bit open system done with Quartus II v12
This project shows the implementation of complex operations of Instruction Set Instructions for NIOS II processor cores.
This core is a low latency divider that works by caching reciprocal values, then using a multiply to perform the divide rather than the usual…
This project is a hardware implementation of a Binary Fully Digital Phase Locked Loop. The loop performance is analyzed theoretically,…
In computing, especially digital signal processing, the multiply–accumulate operation is a common step that computes the product of two numbers…
Facebook
Google
GitHub
Linkedin