A Game Tree is a directed graph whose nodes are states of a game. A game state is a configuration of the game on a specific time. The complete game…
This is a complete 16 Quadrature amplitude modulator and demodulator with output precision of 10 bits (can be increased/decreased by changing the…
The aim of this IP is to provide those who use it the possibility and reading and writing in an external interface for analog devices. Porting APB…
The aim of this project is to provide a set of ARINC-429-compatible TX and RX synthesizable interfaces. The transmitting interface serializes a…
Usually, 8b/10b codec is required with using a fibre-optic SERDES interface. A SERDES converts fast serial optic-stream into less fast 10bit…
Ever needed a pulse at a given frequency ( period ). Well that is what BaudGen gives you. By the use of parameters, you specify the frequency of…
Open Source Documented Verilog UART Purpose This module was created as a result of my own need for a UART (serial line I/O) component and…
E1 framer Deframer core implements CCITT (ITU) recommedations G.704,G.706 and G.732 for 30 channel multiplexed E1 stream at 2.048Mbps rate.…
Since lots of people ask me questions about my core, i want to clarify some things: 1) the master works, the slave is not entirely thought-through,…
The NEC IR transmission protocol decoding circuit. The protocol * a 9ms leading pulse burst (16 times the pulse burst length used for a logical…
The SDSPI controller offered here exports an high level SD card interface to the rest of an FPGA core via a wishbone bus. Interaction at the lower…
This is a VHDL implementation of Triple-DES (pipelined) and DES cryptographic algorithms, as recommended by NIST. In our tests the core has been…
This tool working on WinXP is used to generate verilog-RTL for Reed-Solomon Codec. - Selectable Decoder/Encoder/Both - Symbol width…
This is a wishbone B3 compliant RAM memory. The memory array is defined as a 32 bit memory. This gives two valuable benefits. First. memory array…
Description coming soon.
Wishbone to Parallel FLASH interface with integral wait-state generator. This design has been used with the Intel StrataFlash Xilinx Spartan 3E…
Interface an 8051-compatible microcontroller with the Wishbone bus. Features - Multiplexed 8051 address/data bus to Wishbone Master - Very simple,…
VHDL implementation of the 6530 RRIOT (ROM-RAM-I/O-TIMER) Released under EUPL Licence (LGPL compatible). , ROM (1024 x 8) RAM (64 x 8) Two parallel…
The pipelined architecture is often used in high speed FPGA cores. In complex designs data processing is often splitted into multiple paths…
Clock Domain Crossing micro FIFO (Verilog/SystemVerilog): cdc_ufifo provide an minimalist fifo. Most advantage - not use RAM blocks. it can be 4…
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