This is a date/time keeping core. It uses an external 100,60 or 50 Hz time-of-day signal to update a group of BCD counters which record the date…
This is a Motorola DragonBall/68K to Wishbone bridge. The core translates the 16bit DragonBall/68K bus into a full featured 16bit Wishbone master…
After watching a friend demonstrate how a Raspberry PI GPIO pin could be used to transmit an FM signal for a short distance, I wondered if the…
This is a very small and simple module, which scans through an X-Y matrix of keys, and produces a "snapshot" of bits which represent the…
See video on YouTube: http://www.youtube.com/watch?v=UsYXRPRBsmk
VHDL Implementation of a quadrature decoder module with a Wishbone bus interface. This module has the following features: UPDATED per version…
Poisson process generator. The time between each pair of consecutive pulses has an exponential distribution with desired rate. Тhе auxiliary…
Simple General Purpose IO port. It supports up to 8 GPIO pins. Each pin is individually programmable as either input or output. The core features…
Simple programmable interrupt controller. It supports up to 8 interrupt sources. Polarity and sensitivity (either edge or level) is programmable…
The Intel 4004 was the first commercially-available single-chip CPU. Developed by Intel in 1969 for the Busicom company for use in the Busicom…
The MC68HC08 is a family of low-cost, high-performance 8-bit microcontroller units. It is based on the customer-specified integrated circuit (CSIC)…
The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor. Introduction July 2011: Project copied to…
Navré is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications. Atmel AVR compatible All…
The Open JTAG project has as objetive to give to the public domain a complete hardware and software JTAG project. Based on a simple hardware board,…
This core implements a 16 MB DWord-addressable memory image in the Wishbone bus (so WB width is 32 bit). Its functionality is reduced to the…
Constrained random testing enables us to cover many more system behaviors through random input variations, random fault injections, and automatic…
The project is intended for checking FPGA-based device for high consumption power. Number of parameter gives possibility to change number of used…
Uart2BusTestBench is implemented using Universal Verification Methodology to perform the functional verification to the RTL design released by Moti…
Bilinear demosaicing is a digital image process used to reconstruct a full color image. With the demosaick algorithm it achieves reasonable image…
The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the openMSP430 core.
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