Or try an example search: 3DES
Core1990 is a point-to-point communication protocol using the royalty-free Interlaken protocol as its foundation. It is designed by engineers and…
Please write a description of the project here. It is used as a MetaTag (search engines looks at this).
This is another UART project, but is different because that it is very small and will occupy less macrocells on a CPLD. The purpose of this core is…
Please download source code from: https://github.com/linuxbestlzs
Please write a description of the project here. It is used as a MetaTag (search engines looks at this).
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please check the source code from: https://github.com/linuxbestahci https://github.com/linuxbestahci_mpi
Control the activity and status of your FPGA by targeting a memory mapped space inside it. Based on: -- elements from the GH libraries…
n/a
Open Peer to Peer Interface, Wishbone to Aurora Bridge (OP2P). This interface logic has been designed to provide a very high performance multi-lane…
Main features of latest v5 HW are: -LPC memory read (can be disabled),LPC Firmware Hub memory read and IO write for POST Code capture (and display…
This is a JTAG Master written in VHDL. It's simulated and tested with XC9500 and the jtag slave from opencores (http://opencores.orgproject,jtag)
project is closed at the moment.
This is a receiver for a Multichannel Audio Digital Interface (MADI), also known as AES-10. This type of fibreoptical or electrical connection is…
This core decodes incoming Manchester encoded data. The core is easily modified for your particular project, in that there are just a few constants…
This is a Manchester encoded UART that enables runing small periferals with parasitic power derived from the TXD line, and allowing large clock…
Introduction The system is an Interface between the Analog Digital Converter (ADC) and a PC connected by Ethernet. And the system is based the…
The OPB SPI Core connects a FPGA to a DSP or Microprocessor as Slave-Device. This means all transfers are initiated by the Master an the…
A simple one-wire controller that does not require a CPU to operate. Also included is a higher level DS1820 controller that implements the search,…
opb_usblite - opb_uartlite replacement for Xilinx Microblaze processor written in VHDL and Verilog. The opb_usblite is compatible with the USB CDC…
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