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LinkRunCCA is a real-time single-pass connected component analysis/ connected component labeling (CCA/CCL) implemented in Verilog HDL. It can be…
FIR filter - architecture written with pure verilog - parameterizable in verilog code - cascaded - processing is paralleled - data and coefficients…
CIC filter It is the CIC filter with Hogenauer pruning. This project is based on https://opencores.org/projects/cic_core project. Differences are…
Integer streaming FFT fixed size and resizable. Language - SystemVerilog. Generator of rotation coefficients in MatLab. Includes Quartus project…
Generic FIR filter. Builds optimized filter according to number of multipliers, supports serial or parallel architecture. Supports delays in input.…
Low-pass filter using an FIR Linear-phase structure for more information please view README file.
The PID controller IP core performs digital proportional–integral–derivative controller (PID controller) algorithm. The algorithm first…
Pipelined FFT/IFFT 128 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 128 – complex point…
Pipelined FFT/IFFT 256 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 256 – complex point…
Pipelined FFT/IFFT 64 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 64 – complex point…
Conveyored (result on every clock) elementary functions, implemented with CORDIC for demoscene project (http://www.youtube.comwatch?v=oh1_MzuFtdU).…