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Category: Testing / Verification IP Cores (14)

PRBS Signal Generator And Checker

PRBS Signal Generator And Checker

n/a

License : LGPL
Language : Verilog
SoC Generator Using Verilog

SoC Generator Using Verilog

n/a

License : LGPL
Language : Verilog
Boost Converter in Verilog

Boost Converter in Verilog

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog
CPU-to-FPGA Bus Transaction Monitor with JTAG

CPU-to-FPGA Bus Transaction Monitor with JTAG

A CPU-to-FPGA bus transaction monitor, captures the CPU write/read address/data to/from memory-mapped registers that resides in the FPGA, and…

License : LGPL
Language : Verilog
DS1621 Verilog Model with Testing Tasks

DS1621 Verilog Model with Testing Tasks

DS1621 verilog model with testing tasks. Testing elements assume the existence of the low level write/read (need to be written by the user) and…

License : LGPL
Language : Verilog
Generic AHB Master Stub for 32/64 data bits, AHB Bursts and Random Wait-states

Generic AHB Master Stub for 32/64 data bits, AHB Bursts and Random Wait-states

Generic AHB master stub. Built out of an AXI master and an AXI2AHB bridge. Supports 32/64 data bits, AHB bursts and random wait-states. The design…

License : LGPL
Language : Verilog
Generic AHB Slave Stub for 32/64 data bits, AHB Bursts and Random Wait-states

Generic AHB Slave Stub for 32/64 data bits, AHB Bursts and Random Wait-states

Generic AHB slave stub. Supports 32/64 data bits, AHB bursts and random wait-states. The design is built according to input parameters: address…

License : LGPL
Language : Verilog
Generic APB Master Stub for APB and APB3 Protocols

Generic APB Master Stub for APB and APB3 Protocols

Generic APB master stub. Based on an AXI master stub and an AXI2APB bridge. Supports both APB and APB3 protocols (APB3 is with pready and pslverr…

License : LGPL
Language : Verilog
Generic AXI Slave Stub for 32/64 data bits, AXI Bursts and Random Wait-states

Generic AXI Slave Stub for 32/64 data bits, AXI Bursts and Random Wait-states

Generic AXI slave stub. Supports 32/64 data bits, AXI bursts and random wait-states. The design is built according to input parameters: address…

License : LGPL
Language : Verilog
Generic APB Slave Stub for APB and APB3 Protocols

Generic APB Slave Stub for APB and APB3 Protocols

Generic APB slave stub. Support both APB and APB3 protocols (APB3 is with pready and pslverr). Supports slave error, random and fixed wait-states.…

License : LGPL
Language : Verilog
Generic AXI Master Stub for Multiple AXI IDs, 32/64 data bits, AXI bursts and random wait-states

Generic AXI Master Stub for Multiple AXI IDs, 32/64 data bits, AXI bursts and random wait-states

Generic AXI master stub. Supports multiple internal masters (multiple AXI IDs), 32/64 data bits, AXI bursts and random wait-states. The design is…

License : LGPL
Language : Verilog
Standalone Minimalist i2clcd IP Core

Standalone Minimalist i2clcd IP Core

i2clcd is a minimalist i2clcd IP core that provides the basic framework for the implementation of custom i2clcd devices. The core provides a means…

License : LGPL
Language : Verilog
Universal Asynchronous Receiver/Transmitter (UART) observer

Universal Asynchronous Receiver/Transmitter (UART) observer

This module observes binary inputs, representing them in a user-friendly way inside UART terminal. The output is formatted, human readable and the…

License : LGPL
Language : Verilog
Wishbone Accessible Scope | Logic Analyzer

Wishbone Accessible Scope | Logic Analyzer

This is a wishbone accessible scope or logic analyzer. Connect this scope internally to your favorite 32-bits of information from internal to your…

License : GPL
Wishbone Version : B.4
Language : Verilog