All About Circuits

Search our IC Design Center for IP Cores and IC Design Related Content.

Or try an example search: 8 bit multiplier

Filters

Category: Video Controller IP Cores (20)

AXI4 To VGA Frame Buffer With Linux Driver

AXI4 To VGA Frame Buffer With Linux Driver

This design is very simple in one verilog file. There is 2 version of the design : RGB332 (one pixel is one byte) and RGB565 (one pixel is 2 bytes)…

License : LGPL
Language : Verilog
Altera Cyclone III 3C120 Video Stream Scaler

Altera Cyclone III 3C120 Video Stream Scaler

The Video Stream Scaler scales streaming video up or down in resolution. Bilinear and nearest neighbor resize modes are supported. This core…

License : LGPL
Language : Verilog
Low-Power Real-time H.264/AVC Baseline Decoder

Low-Power Real-time H.264/AVC Baseline Decoder

Overview Nova is a low-power realtime H.264/AVC baseline decoder of QCIF resolution, targeting mobile applications. It is a dedicated, full…

Language : Verilog
16x2 LCD Display Module Using Verilog

16x2 LCD Display Module Using Verilog

There are a great many 16x2 LCD displays available to electronic design engineers. Nearly all of them are controlled by the Hitachi HD44780 control…

License : LGPL
Language : Verilog
MPEG2 to RGB Video Output Decoder

MPEG2 to RGB Video Output Decoder

This project is an MPEG2 video decoder. The decoder converts an MPEG2 stream into a RGB video output. To get a functioning decoder, you will need…

License : BSD
Language : Verilog
FPGA Implementation JPEG Encoder Verilog

FPGA Implementation JPEG Encoder Verilog

This core takes as an input the red, green, and blue pixel values, like from a tiff image file, and creates the JPEG bitstream necessary to build a…

License : LGPL
Language : Verilog
FastMemoryLink Minimal VGA Framebuffer Controller

FastMemoryLink Minimal VGA Framebuffer Controller

This core is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications. Minimal VGA…

License : GPL
Language : Verilog
High Performance Image Warping/Texture Mapping Core

High Performance Image Warping/Texture Mapping Core

Texture mapping unit tailored for Milkdrop acceleration. This core was designed for Milkymist, a highly integrated opensource VJing platform. See…

License : Others
Language : Verilog
TFT LCD Display Controller

TFT LCD Display Controller

Progress - Display one repeat line (800 pixels) stored in ROM synthesized in FPGA. - Self-display word block (designed). - (Have problem on…

License : GPL
Language : Verilog
LCD to HDMI Output Interface IP

LCD to HDMI Output Interface IP

This is an LCD to HDMI converter that is tested on NexusVideo board from DIGILENT. Is a generic IP that do not necesitate any setup, only take the…

License : LGPL
Language : Verilog
OPB-compatible VGA Character Display for Spartan Development Board

OPB-compatible VGA Character Display for Spartan Development Board

This is an OPB-compatible VGA character display for the Spartan 3E development board, which does not contain DACs. The core is very small,…

License : GPL
Language : Verilog
RTF Bitmap Multiple Display Controllers

RTF Bitmap Multiple Display Controllers

Video frame buffer. This core is a low to medium resolution bitmap display controller. It was engineered for use on the Nexsys2 board, a Spartan3e…

License : LGPL
Language : Verilog
RTF Sprite Controller | Hardware Cursors

RTF Sprite Controller | Hardware Cursors

There is a new sprite controller which operates differently from the original. The original used image caches and supported a color depth up to 32k…

License : LGPL
Language : Verilog
All-in-One RTF Text Display Controller

All-in-One RTF Text Display Controller

An all-in-one text / bitmap / sprite controller (FT_VIC.v) is in the works. It will use a 640x400 video mode, fixed 80x50 char text display,…

License : LGPL
Language : Verilog
Wire-Frame 3D Graphics Rendering Accelerator IP Core

Wire-Frame 3D Graphics Rendering Accelerator IP Core

WF3D is a real-time 3D graphics rendering IP Core. The IP Core reads 3D triangle vertices from memory, then transforms them into 2D space, and…

License : BSD
Language : Verilog
Sinclair ULA chip Implementation for ZX Spectrum Microcomputers

Sinclair ULA chip Implementation for ZX Spectrum Microcomputers

This is an implementation of the Sinclair ULA chip, found in ZX Spectrum microcomputers. The project offers various implementations: both FPGA…

License : GPL
Language : Verilog
Wishbone revB.3 Compliant VGA/LCD Video Controller

Wishbone revB.3 Compliant VGA/LCD Video Controller

The OpenCores VGA/LCD Controller core is a WISHBONE revB.3 compliant embedded VGA core capable of driving CRT and LCD displays. It supports user…

License : GPL
Language : Verilog
Demosaic (Bilinear)

Demosaic (Bilinear)

Bilinear demosaicing is a digital image process used to reconstruct a full color image. With the demosaick algorithm it achieves reasonable image…

License : LGPL
Language : Verilog
OpenGFX430

OpenGFX430

The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the openMSP430 core.

License : BSD
Language : Verilog
Yet Another Verilog VGA

Yet Another Verilog VGA

A simple VGA controller written in Verilog. I just add a pixel handler for simplicity.

License : LGPL
Language : Verilog