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Category: Communication Controller IP Cores (133)

Core1990 : Royalty-free Interlaken Protocol

Core1990 : Royalty-free Interlaken Protocol

Core1990 is a point-to-point communication protocol using the royalty-free Interlaken protocol as its foundation. It is designed by engineers and…

License : LGPL
Language : VHDL
IEEE 802.3-2008 Clause 36 PCS 1000BASE-X

IEEE 802.3-2008 Clause 36 PCS 1000BASE-X

Verilog implementation of IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS) type 1000BASE-X (1000baseLX and/or 1000baseSX)

License : LGPL
Language : Verilog
10/100M Ethernet-FIFO Convertor

10/100M Ethernet-FIFO Convertor

Flow Summary Compiled in Quartus 9.0 +-------------------------------------------------------------------------------+ ; Flow Summary ;…

License : LGPL
Language : Verilog
10/100/1000 Mbps tri-mode Ethernet MAC Controller

10/100/1000 Mbps tri-mode Ethernet MAC Controller

mail group is added to track all the Q&A from the author. If you have any question about the design, please send your question to mail group.…

License : LGPL
Language : Verilog
100 Mbps Ethernet MAC Layer Switch

100 Mbps Ethernet MAC Layer Switch

Ethernet MAC Layer Switch. The switch receive 100 MB/s data rate from 6 channels and direct each frame received to its destination port. The switch…

License : LGPL
Language : Verilog
Ethernet 100/1000 Mbps

Ethernet 100/1000 Mbps

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL
Ethernet 10GE MAC

Ethernet 10GE MAC

The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae. Features 1. Interfaces - XGMII…

License : LGPL
Language : Verilog
Minimal UART Core

Minimal UART Core

This is another UART project, but is different because that it is very small and will occupy less macrocells on a CPLD. The purpose of this core is…

License : LGPL
Language : VHDL
Lzs

Lzs

Please download source code from: https://github.com/linuxbestlzs

License : LGPL
Language : Verilog & VHDL
SPORT Interface

SPORT Interface

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog
UDP/IP Core

UDP/IP Core

VHDL implementation of a UDP/IP core! Area-optimized for direct PC-FPGA communication! An advanced/versatile version of the core is included in the…

License : GPL
Language : VHDL
USB To UART

USB To UART

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog
1G Ethernet DPI in Verilog

1G Ethernet DPI in Verilog

Current project provides idea of complex network design verification via [{Linux-tunnel interface} + SystemVerilog DPI-C}].

License : LGPL
Language : Verilog
1G Ethernet ARP Communication Controller FPGA

1G Ethernet ARP Communication Controller FPGA

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL
A Generic VHDL 8b/10b Protocol Encoder and Decoder

A Generic VHDL 8b/10b Protocol Encoder and Decoder

This project, written in generic synthesizable VHDL, provides two separate cores for encoding and decoding byte data according to the 8b/10b…

License : GPL
Language : VHDL
Ethernet Switch on Configurable Logic

Ethernet Switch on Configurable Logic

n/a

License : LGPL
Language : VHDL
Ethernet MAC 10/100 Mbps for CSMA/CD LAN

Ethernet MAC 10/100 Mbps for CSMA/CD LAN

The Ethernet MAC (Media Access Control), sublevel within the Data Link Layer of the OSI reference model. This core is designed for implementation…

License : LGPL
Language : Verilog
Another Wishbone Controlled UART

Another Wishbone Controlled UART

Forasmuch as many have taken in hand to set forth a UART core, ... It seemed good to me also, having had perfect (a good) understanding of all…

License : GPL
Wishbone Version : B.4
Language : Verilog
APB SPI Design Transmission

APB SPI Design Transmission

APB SPI design is meant to be interfaced with slow-speed peripherals. The initial design will contain APB slave on one side, which will initiate…

License : LGPL
Language : Verilog
SATA AHCI Controller Drivers

SATA AHCI Controller Drivers

please check the source code from: https://github.com/linuxbestahci https://github.com/linuxbestahci_mpi

License : LGPL
Language : Verilog & VHDL