All About Circuits

Search our IC Design Center for IP Cores and IC Design Related Content.

Or try an example search: 3DES

Filters

Category: Memory Core IP Cores (35)

8/16/32 bit Configurable SDRAM Controller

8/16/32 bit Configurable SDRAM Controller

Feature: • 8/16/32 Configurable SDRAM data width • Wish Bone compatible • Application clock and SDRAM clock can be async •…

License : GPL
Language : Verilog
DDR2-SDRAM Controller on Xilinx Spartan-3A

DDR2-SDRAM Controller on Xilinx Spartan-3A

This project implements a DDR2-SDRAM Controller on a Xilinx Spartan-3A Board Function After a Power on : ================== 1. Init-Sequenz for the…

License : LGPL
Language : VHDL
16-bit SDRAM Controller Chip for Wishbone Interface

16-bit SDRAM Controller Chip for Wishbone Interface

This IP core is that of a small, simple SDRAM controller used to provide a 32-bit pipelined Wishbone interface to a 16-bit SDRAM chip. When…

License : GPL
Language : Verilog
2Q Cache Strategy on VHDL

2Q Cache Strategy on VHDL

Overview I implemented 2Q cache strategy from paper "2Q: A Low Overhead High Performance Buffer Management Replacement Algorithm" written…

License : LGPL
Language : VHDL
Asynchronous Wishbone Compatible SDRAM Controller

Asynchronous Wishbone Compatible SDRAM Controller

SUPERSEDED BY HPDMC. Please do not ask me about this core! It is old and totally unsupported. HPDMC support, however, is available from the…

License : GPL
Language : Verilog
BRSFmnCE FPGA Implementation

BRSFmnCE FPGA Implementation

This module implements a synchronous FIFO using Block RAM resources such as those found in SRAM-based FPGAs. This module has been used in several…

License : LGPL
Language : Verilog
32-bit CFI Flash Controller IP

32-bit CFI Flash Controller IP

CFI flash controller IP. Provides two modes of operation - simple (Wishbone bus straight through to flash bus, essentially, but with 32-bit word…

License : LGPL
Language : Verilog
Implementation of DDR3 SDRAM Controller for FPGAs (Controller Core)

Implementation of DDR3 SDRAM Controller for FPGAs (Controller Core)

This is a controller core for DDR3 SDRAM. Default configuration supports one 64 bit UDIMM or SO-DIMM Supports DIMM sizes of 1GB, 2GB, 4GB and 8GB…

License : LGPL
Language : Verilog
DDR2 mem controller for Digilent Genesys Board

DDR2 mem controller for Digilent Genesys Board

n/a

License : LGPL
Language : Verilog
FAT32 File System Parser

FAT32 File System Parser

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL
Configurable Direct Mapped Cache Controller

Configurable Direct Mapped Cache Controller

This project is to develop a direct mapped cache controller for embedded applications. Key Design Features - Direct mapped with configurable…

License : LGPL
Language : Verilog
DPSFmnCE FIFO for UARTs

DPSFmnCE FIFO for UARTs

This project provides a parameterizable synchronous FIFO which uses LUTs instead of Block RAMs for its memory. The FIFO can be parameterized in…

License : LGPL
Language : Verilog
High Performance Dynamic Memory Controller (HPDMC)

High Performance Dynamic Memory Controller (HPDMC)

HPDMC is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications. Fast DDR SDRAM controller…

License : GPL
Language : Verilog
Functional RAM Simulation Models

Functional RAM Simulation Models

The simu_mem project provides functional simulation models of commercially available RAMs. Advantages of the simu_mem models…

License : LGPL
Language : VHDL
Generic FIFO in VHDL

Generic FIFO in VHDL

A very generic implementation of a FIFO. Makes good use of VHDL transactors for data transfers. Does not support Wishbone yet, but it's planned.

License : LGPL
Language : VHDL
Wishbone Wrapper for Xilinx Memory Interface Generator (MIG)

Wishbone Wrapper for Xilinx Memory Interface Generator (MIG)

Two WISHBONE wrappers will be developed for Xilinx Memory Interface Generator (MIG). The first is compliant with version B4 Registered Feedback…

License : LGPL
Language : Verilog
openHMC Controller - Configurable Open-Source Hybrid Memory Cube

openHMC Controller - Configurable Open-Source Hybrid Memory Cube

openHMC is an open-source project developed by the Computer Architecture Group (CAG) at the University of Heidelberg in Germany. It is a…

License : LGPL
Language : Verilog
NAND Controller (ONFI compliant)

NAND Controller (ONFI compliant)

n/a

License : LGPL
Language : VHDL
OPB PSRAM Controller

OPB PSRAM Controller

The OPB PSRAM-Controller connect a Pseudo-Staic-RAM, also named CellularRAM™ to the OPB-Bus. Features Design - max. 80 Mhz Memory Clock for a…

License : GPL
Language : VHDL
Open FreeList Module

Open FreeList Module

Open FreeList Readme General Description The Open FreeList module is used to manage a set of variable sized packets inside a fixed memory block.…

License : LGPL
Language : Verilog