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Category: Uncategorized IP Cores (23)

Configurator

Configurator

This application parses a Verilog define file and presents a GUI to the user


License : LGPL
Language : Verilog
2D Game Console on Altera DE2-115

2D Game Console on Altera DE2-115

A platform for execute simple games, with graphics in two dimensions, implemented on Altera DE2-115 development board. • Compatible with Sega…


License : LGPL
Language : Verilog & VHDL
Adjustable Frequency Divider

Adjustable Frequency Divider

Usage and Operation In order to operate the circuit correctly it must first be reset (asynchronously). Below is a timing diagram that illustrates…


License : LGPL
Language : Verilog
Avalon to Wishbone Bridge

Avalon to Wishbone Bridge

AVALON/WISHBONE Bridge This is an Avalon to WishBone Bridge. Avalon is a bus standard mainly used in Altera(Now Intel) Tools. Wishbone as every one…


License : LGPL
Wishbone Version : B.4
Language : Verilog
Bubble Sort Module in Verilog

Bubble Sort Module in Verilog

simple fast bubble sort module in verilog


License : LGPL
Language : Verilog
DNA Sequence Alignment Accelerator

DNA Sequence Alignment Accelerator

This is an easily configurable systolic array of processors to compute the optimal alignment between two DNA sequences. It supports affine gap…


License : LGPL
Language : Verilog
Cray-2-Reboot for FPGAs

Cray-2-Reboot for FPGAs

Files also located at: https://github.com/DarkwaveTechnologiesCray-2-Reboot The goal of this project is to make a clock and gate equivalent…


License : LGPL
Language : Verilog
Verilog Code LCD Block

Verilog Code LCD Block

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).


License : LGPL
Language : Verilog
Interrupt Controller 68000

Interrupt Controller 68000

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).


License : LGPL
Language : Verilog
OPL3 20 - Yamaha OPL3 (YMF262) FM Synthesizer Chip

OPL3 20 - Yamaha OPL3 (YMF262) FM Synthesizer Chip

Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer chip. Design is complete and working on the Digilent ZYBO…


License : LGPL
Language : Verilog
PSG16 Audio Interface Circuit

PSG16 Audio Interface Circuit

PSG32 is an audio interface circuit (sound interface device) for use within a programmable system to interface the system to an audio output. It…


License : LGPL
Language : Verilog
Pulse Width Modulator with 16-bit Main Counter

Pulse Width Modulator with 16-bit Main Counter

Pulse Width Modulator Features • Work as one PWM or one timer. • 16 bits main counter. • PWM/Timer can choose between Wishbone…


License : LGPL
Language : Verilog
Quadrature Rotary Encoder and Low-pass Filter

Quadrature Rotary Encoder and Low-pass Filter

Module receives A and B quadrature signals from incremental angular sensor and counts relative angular position. Angular resolution is 4 counts per…


License : LGPL
Language : Verilog
Simple Linear Digital Automatic Gain Control (AGC)

Simple Linear Digital Automatic Gain Control (AGC)

Simple linear digital automatic gain control. More info: https://www.embedded.com/print/4214571


License : LGPL
Language : Verilog
Status LED - Simple Module for On Board Heartbeat LED

Status LED - Simple Module for On Board Heartbeat LED

A simple module to get the most of your on board heartbeat LED. Change or add more sequences easily in parameters file.


License : LGPL
Language : Verilog
SystemC/Verilog Random Number Generator

SystemC/Verilog Random Number Generator

A SystemC/Verilog random number generator based on the combination of a LFSR and a CASR with very good statistical properties. Based on the Thomas…


License : LGPL
Language : Verilog
Virtual RS232 Terminal with LVDS LCD Controller

Virtual RS232 Terminal with LVDS LCD Controller

An Virtual RS232 Terminal developed with Avnet Xilinx Spartan 3A Evaluation Kit ( Spartan XC3S400A ) that has a LVDS LCD Controller (Notebook LCD…


License : LGPL
Language : Verilog
Data unConfuser Engine

Data unConfuser Engine

Hi, Everyone, You can find detailed information about project in this pdf. The pdf explains most of the things about the project like: 1. Port list…


License : LGPL
Language : Verilog
Veristruct - an IEEE1364.1995 Preprocessor

Veristruct - an IEEE1364.1995 Preprocessor

Overview Veristruct is an an IEEE1364.1995 preprocessor that adds some C-style struct support to the Verilog language. It takes as input Veristruct…


License : LGPL
Language : Verilog
AHB Master to WishBone Slave Bridge

AHB Master to WishBone Slave Bridge

A AHB master to WishBone slave bridge along with a basic testbench is included. Burst in not yet supported.


License : LGPL
Language : Verilog