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Category: All IP Cores (1032)

10/100/1000 Mbps tri-mode Ethernet MAC Controller

10/100/1000 Mbps tri-mode Ethernet MAC Controller

mail group is added to track all the Q&A from the author. If you have any question about the design, please send your question to mail group.…

License : LGPL
Language : Verilog
100 Mbps Ethernet MAC Layer Switch

100 Mbps Ethernet MAC Layer Switch

Ethernet MAC Layer Switch. The switch receive 100 MB/s data rate from 6 channels and direct each frame received to its destination port. The switch…

License : LGPL
Language : Verilog
10G Ethernet MAC Core with IEEE 802.3ae Compliant

10G Ethernet MAC Core with IEEE 802.3ae Compliant

The 10G ethernet mac core. It is compliant with ieee 802.3ae. Our plan is: 1. reading specification 2. observation of different companies 10g…

Language : Verilog
E1-G.703,G.704,G.706 Framer/deframer

E1-G.703,G.704,G.706 Framer/deframer

Features - feature1 - feature2 Status Ready for downloading via CVS. Path: e1framer

Ethernet 100/1000 Mbps

Ethernet 100/1000 Mbps

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL
General-Purpose I/O (GPIO) Core

General-Purpose I/O (GPIO) Core

The GPIO IP core is user-programmable general-purpose I/O controller. Its use is to implement functions that are not implemented with the dedicated…

Ethernet 10GE MAC

Ethernet 10GE MAC

The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae. Features 1. Interfaces - XGMII…

License : LGPL
Language : Verilog
Minimal UART Core

Minimal UART Core

This is another UART project, but is different because that it is very small and will occupy less macrocells on a CPLD. The purpose of this core is…

License : LGPL
Language : VHDL
Lzs

Lzs

Please download source code from: https://github.com/linuxbestlzs

License : LGPL
Language : Verilog & VHDL
SPORT Interface

SPORT Interface

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog
UDP/IP Core

UDP/IP Core

VHDL implementation of a UDP/IP core! Area-optimized for direct PC-FPGA communication! An advanced/versatile version of the core is included in the…

License : GPL
Language : VHDL
USB To UART

USB To UART

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog
Fast AES-128 Encryption Only Cores

Fast AES-128 Encryption Only Cores

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : Others
Language : Verilog
HIGHT Crypto Core

HIGHT Crypto Core

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog
802.3an LDPC Decoder

802.3an LDPC Decoder

LDPC decoder for 10GBase-T Ethernet (802.3an), based on Gallager's A algorithm. See also…

Language : Verilog
Constellation Encoder

Constellation Encoder

Features - feature1 - feature2 Status - ... - ...

Reed Solomon Encoder/Decoder

Reed Solomon Encoder/Decoder

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog
Configurator

Configurator

This application parses a Verilog define file and presents a GUI to the user

License : LGPL
Language : Verilog
Gsc

Gsc

Description of project.. Features - feature1 - feature1.1 -feature1.2 -feature2

License : GPL
Language : Verilog
2D Game Console on Altera DE2-115

2D Game Console on Altera DE2-115

A platform for execute simple games, with graphics in two dimensions, implemented on Altera DE2-115 development board. • Compatible with Sega…

License : LGPL
Language : Verilog & VHDL