All About Circuits

Category: All IP Cores (1032)

1G Ethernet DPI in Verilog

1G Ethernet DPI in Verilog

Current project provides idea of complex network design verification via [{Linux-tunnel interface} + SystemVerilog DPI-C}].


License : LGPL
Language : Verilog
1G Ethernet ARP Communication Controller FPGA

1G Ethernet ARP Communication Controller FPGA

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).


License : LGPL
Language : VHDL
VHDL Standard 16550 UART Core

VHDL Standard 16550 UART Core

A UART that is compatible with the industry standard 16550D Includes wrappers for the Wishbone and AMBA APB busses Features Uses parts from the…


Language : VHDL
A Generic VHDL 8b/10b Protocol Encoder and Decoder

A Generic VHDL 8b/10b Protocol Encoder and Decoder

This project, written in generic synthesizable VHDL, provides two separate cores for encoding and decoding byte data according to the 8b/10b…


License : GPL
Language : VHDL
Ethernet Switch on Configurable Logic

Ethernet Switch on Configurable Logic

n/a


License : LGPL
Language : VHDL
A VHDL CAN Protocol Controller

A VHDL CAN Protocol Controller

A (as far as I know) untested VHDL translation of the Verilog Can protocol Controller To Download, click at the "Downloads" button upper…


Language : VHDL
ADAT Lightpipe Optical Datastream Receiver

ADAT Lightpipe Optical Datastream Receiver

This is a feed forward receiver for an ADAT lightpipe optical datastream. This type of multichannel audio connection is widely used in professional…


Language : VHDL
AMI and HDB1 Line Codes in VHDL Implementation

AMI and HDB1 Line Codes in VHDL Implementation

VHDL implementation of the AMI --- Alternate Mark Inversion --- and HDB1 --- High Density Bipolar of order 1 line codes. For other line code refer…


Language : VHDL
Ethernet MAC 10/100 Mbps for CSMA/CD LAN

Ethernet MAC 10/100 Mbps for CSMA/CD LAN

The Ethernet MAC (Media Access Control), sublevel within the Data Link Layer of the OSI reference model. This core is designed for implementation…


License : LGPL
Language : Verilog
Another Wishbone Controlled UART

Another Wishbone Controlled UART

Forasmuch as many have taken in hand to set forth a UART core, ... It seemed good to me also, having had perfect (a good) understanding of all…


License : GPL
Wishbone Version : B.4
Language : Verilog
APB SPI Design Transmission

APB SPI Design Transmission

APB SPI design is meant to be interfaced with slow-speed peripherals. The initial design will contain APB slave on one side, which will initiate…


License : LGPL
Language : Verilog
SATA AHCI Controller Drivers

SATA AHCI Controller Drivers

please check the source code from: https://github.com/linuxbestahci https://github.com/linuxbestahci_mpi


License : LGPL
Language : Verilog & VHDL
Asynchronous SPI Master in Verilog

Asynchronous SPI Master in Verilog

This is a Verilog language asynchronous SPI, this mean that the controller can have a different clock frequency than SPI module. On the simulate…


License : LGPL
Language : Verilog
Automatic BAUD Rate Generator

Automatic BAUD Rate Generator

This module scans an incoming stream of rs232 serial characters. It constantly looks for a new character, which it detects by seeing the…


Verilog Bitwise Addressable GPIO

Verilog Bitwise Addressable GPIO

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).


License : LGPL
Language : Verilog
Bluespec 802.11a Transmitter Baseband

Bluespec 802.11a Transmitter Baseband

802.11a Transmitter Baseband in BSV This package implements a parameterized baseband hardware logic for an 802.11a Transmitter. This project has…


License : LGPL
Language : Bluespec
Free Bluetooth Baseband Controller

Free Bluetooth Baseband Controller

The Bluetooth is a standard protocol for wireless connection between devices such as cell phones, PDAs, PCs and any other device. The main…


CAN IP Protocol Controller for Broadcast Communication

CAN IP Protocol Controller for Broadcast Communication

Controller Area Network or CAN is a control network protocol from Bosch that has found wide use in Industrial Automation and the Automotive…


Cheap Ethernet Interface for FPGAs

Cheap Ethernet Interface for FPGAs

Cheap Ethernet interface Realization of Ethernet interface and protocols optimized for minimal external components and FPGA resources. FPGA may…


License : LGPL
Language : Verilog
Discrete Multi Tone - DMT Transceiver for ADSL Systems

Discrete Multi Tone - DMT Transceiver for ADSL Systems

Discrete Multi Tone (DMT) is the modulation scheme used for Asymmetric Digital Subscriber Line (ADSL) systems and one of the modulation schemes…


License : GPL
Language : Other