DQPSK symbol mapper suitable for TETRA/APCO-25 physical layer.
This core is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications. DMX protocol fully…
This Module is EPP v1.9 and can communicate with a computer parallel port. It is memory less module and has got two bits to tell the module user…
This is a fork of the xge_mac and was released by the Computer Architecture Group (http://cag.uni-hd.de) of the University of Heidelberg. Main…
Overview The Serial Media Independent Interface, SMMI, is a low pin count version of the MII normally used between ethernet MAC and PHY. The Serial…
Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE…
Description of project.. This design is Wishbone compatible I2C core. This core can work as I2C master as well as slave. VMM Test-bench is also…
It's a general purpose Cypress EZUSB communication core which was developed for ZTEX FPGA Boards and supports the following features: EZ-USB…
This project implements the simple and light protocol for transmission of data from low resources FPGA connected to the Ethernet PHY and an…
*NOTE* This project is currently unmaintained and uncompleted. If you would like to take over this project please contact the current maintainer.…
Control the activity and status of your FPGA by targeting a memory mapped space inside it. Based on: -- elements from the GH libraries…
The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style…
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This project contains a collection of cores that interface with various gamepads. Each gamepad type has a dedicated controller core which handles…
This component provides a bridge from a FTDI asynchronous FIFO interface (such as found on the FT245R or FT2232) to a Wishbone master interface…
I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the…
The IICMB core provides low-speed, two-wire, bidirectional serial bus interfaces compliant to industry standard I2C protocol. The key feature of…
Project content: trunk/vhdl - source of this open core trunk/prototype_1 - example prototype using the GPIB core trunk/prototype_1/fpga - xilinx…
This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T…
A HyperTransport Tunnel controller written in SystemC. HyperTransport (HT) is a high-performance chip-to-chip interconnect architecture. A tunnel…
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