All About Circuits

Filters

Category: All IP Cores (1032)

HDLC Controller

HDLC Controller

Features - 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame…

I2C Slave in Full Icarus Verilog

I2C Slave in Full Icarus Verilog

i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the implementation of custom I2C slave devices. The core provides…

License : GPL
Language : Verilog
Generic SGMII with 88E1111 Phy

Generic SGMII with 88E1111 Phy

Generic SGMII / 1000X module that can be connected to any transceiver technology. This core has been verified with 88E1111 Phy - Autonegotiation -…

License : GPL
Language : Verilog
I2C Slave to Wishbone Master Interface

I2C Slave to Wishbone Master Interface

I2C slave to WishBone master interface.

License : LGPL
Language : Verilog
I2C Repeater in SystemVerilog

I2C Repeater in SystemVerilog

This is a quick module I hacked together to connect two I2C buses to work around a hardware bug on a board. It mostly works, and I'm posting it…

License : LGPL
Language : Verilog
IEEE 802.15.4 Standard (TX,RX) Physical Layer in VHDL

IEEE 802.15.4 Standard (TX,RX) Physical Layer in VHDL

VHDL implementation of the physical layer of the IEEE 802.15.4 standard (TX, RX). The doc/ directory of the repository contains the thesis related…

License : GPL
Language : VHDL
I2C Bus Traffic Logger

I2C Bus Traffic Logger

FEATURES - Captures I2C 2 wire serial bus activities into an external RAM - Applicable to Atmel 2 wire serial bus format: This includes (1) Random…

I2C GPIO Expander Board Using Verilog Code

I2C GPIO Expander Board Using Verilog Code

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog
OP2P (Open Peer to Peer Interface) Wishbone Aurora Bridge

OP2P (Open Peer to Peer Interface) Wishbone Aurora Bridge

Open Peer to Peer Interface, Wishbone to Aurora Bridge (OP2P). This interface logic has been designed to provide a very high performance multi-lane…

License : LGPL
Language : VHDL
I2S 3-Wire Interface for Audio Streaming

I2S 3-Wire Interface for Audio Streaming

I2S is an industry standard (invented by Philips) 3-wire interface for streaming stereo audio between devices. Typical applications include digital…

License : GPL
Language : VHDL
LPC ROM Emulator on USB Dongle Core

LPC ROM Emulator on USB Dongle Core

Main features of latest v5 HW are: -LPC memory read (can be disabled),LPC Firmware Hub memory read and IO write for POST Code capture (and display…

License : LGPL
Language : VHDL
I2S to Paralell ADC/DAC Controller

I2S to Paralell ADC/DAC Controller

I2S to Paralell ADC/DAC controller This provides a bridge between a paralell device (such as a microcontroller (uC) and an I2S (!not! I2C) audio…

License : GPL
Language : VHDL
I2S Serial Device to Parallel Interface

I2S Serial Device to Parallel Interface

I2S to Parallel Interface This module provides a bridge between an I2S serial device (audio ADC, S/PDIF Decoded data) and a parallel device…

License : GPL
Language : VHDL
Verilog I2S Controller to Wishbone Interface

Verilog I2S Controller to Wishbone Interface

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog
i8255 PPI Realisation Verilog for FPGA

i8255 PPI Realisation Verilog for FPGA

Complete implementation of i8255 PPI in fpga. You may find some datasheets about here. Verilog code has some modules: PORTS - matches to the a,b,c.…

License : LGPL
Language : Verilog
IrDA UART Core for IrDA Communications

IrDA UART Core for IrDA Communications

IrDA core that utilizes uart16550 core for 115.2Kbit/s IrDA communication. Required bit encoding/decoding is performed. The 115.2 (SIR) mode should…

EEE 802.15.4 CRC in VHDL Implementation

EEE 802.15.4 CRC in VHDL Implementation

VHDL implementation of the CRC check in IEEE 802.15.4 (MAC layer).

License : GPL
Language : VHDL
IPv4 Ethernet Packet Creator and Transmitter

IPv4 Ethernet Packet Creator and Transmitter

VHDL implementation of a component that can be connected to the input port of the Virtex-5 Ethernet MAC Local Link Wrapper and that allows for…

License : GPL
Language : VHDL
ISO7816 3 Master on FPGA

ISO7816 3 Master on FPGA

This project aims at implementing a basic iso7816:3 master which can be controlled by software or by a state machine. This is a work in progress.…

License : BSD
Language : Verilog
OFDM Modem IP Core

OFDM Modem IP Core

The main file is modem.vhd I don't separate the test part from modulation part. The main modulation part is ofdm.vhd, and you can chose if it…

Language : VHDL