Please write a description of the project here. It is used as a MetaTag (search engines looks at this).
The lfsr core is a random number generator based on linear feedback shift register(LFSR).The sequence generated has the maximum length possible.The…
A fast (single-cycle) base-2 log function, based on the description at http://www.cantares.on.caextras.html Need an electronic design solution?…
the aim of this design to build combinatorial digital circuit to find in fast parallel the maximum or the minimum of set of given set data where…
Core1990 is a point-to-point communication protocol using the royalty-free Interlaken protocol as its foundation. It is designed by engineers and…
Please write a description of the project here. It is used as a MetaTag (search engines looks at this).
A quick & simple mod 3 calculator(only just combinational logic). the input 8-bit data is divided by 3. and the output is only 0, 1, or 2. I…
QFP32 Arithmetic Core implements a full customizable arithmetic core using the QFP32 format. Available arithmetic operations are easily configured…
// number sorting device, sequential, 2*N clocks for N // linear buffer implementation // sequential, stable, can be partly readed, decreasing…
SystemVerilog: y = sqrt(x); x, y - unsigned integers. Parameterizable streaming integer square root function by the digit-by-digit method.
Parameterizable Verilog module that calculate sum of N variables. It works in streaming mode and can used in convolution (FIR) and in phased array…
Ray Tracing : A rendering technique that challenges anyone who is interested in Computer Science, Computer Graphics and Digital Systems in General.…
VHDL Implementation of a basic Pipeline MIPS processor. It has a translator of MIPS assembler code and implement the division algorithm restoring.
This project implements a simple parametrized FFT engine. The user may define length of FFT (fftlen equal to a power of 2), and may also define the…
Please write a description of the project here. It is used as a MetaTag (search engines looks at this).
C code for generating a stand-alone population counter with user-defined size (number of input bits) and latency (number of clock cycles) in VHDL.
Module of parameterized encoder based on verilog. Synthesized to multi-input OR elements. Example of 16 to 4 priority encode: parameter…
The module expects ASCII character code (in 8-bit binary) and displays the coresponding character on single digit 14-segment monocolor LED display.…
Before You read This is a brief overview of the article about the series of multiplication algorithms. For comparison and estimation of proposed…
Please write a description of the project here. It is used as a MetaTag (search engines looks at this).