Category: All IP Cores (1032)

LCD162B Behavior Model in VHDL

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License : LGPL
Language : VHDL

LFSR Core - Random Number Generator

The lfsr core is a random number generator based on linear feedback shift register(LFSR).The sequence generated has the maximum length possible.The…

License : LGPL
Language : VHDL

Fast Base-2 Log Function in Single-Cycle

A fast (single-cycle) base-2 log function, based on the description at http://www.cantares.on.caextras.html Need an electronic design solution?…

License : LGPL
Language : Verilog

Maximum/Minimum Binary Tree Finder

the aim of this design to build combinatorial digital circuit to find in fast parallel the maximum or the minimum of set of given set data where…

License : LGPL
Language : VHDL

Core1990 : Royalty-free Interlaken Protocol

Core1990 is a point-to-point communication protocol using the royalty-free Interlaken protocol as its foundation. It is designed by engineers and…

License : LGPL
Language : VHDL

MODBUS Implementation in VHDL

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License : LGPL
Language : VHDL

Simple Mod 3 Calculator

A quick & simple mod 3 calculator(only just combinational logic). the input 8-bit data is divided by 3. and the output is only 0, 1, or 2. I…

License : LGPL
Language : Verilog

QFP32 (QuadFixedPoint32) Arithmetic Unit

QFP32 Arithmetic Core implements a full customizable arithmetic core using the QFP32 format. Available arithmetic operations are easily configured…

License : LGPL
Language : VHDL

Number Sorting Device O (N)

// number sorting device, sequential, 2*N clocks for N // linear buffer implementation // sequential, stable, can be partly readed, decreasing…

License : LGPL
Language : Verilog

Parameterizable Integer Square Root by Digit-by-digit Method

SystemVerilog: y = sqrt(x); x, y - unsigned integers. Parameterizable streaming integer square root function by the digit-by-digit method.

License : LGPL
Language : Verilog

Verilog Parameterizable Adder Tree

Parameterizable Verilog module that calculate sum of N variables. It works in streaming mode and can used in convolution (FIR) and in phased array…

License : LGPL
Language : Verilog

Ray Tracing Rendering Engine

Ray Tracing : A rendering technique that challenges anyone who is interested in Computer Science, Computer Graphics and Digital Systems in General.…

License : LGPL
Language : VHDL

Pipeline MIPS Processor in VHDL

VHDL Implementation of a basic Pipeline MIPS processor. It has a translator of MIPS assembler code and implement the division algorithm restoring.

License : GPL
Language : VHDL

Simple Parametrized FFT Engine

This project implements a simple parametrized FFT engine. The user may define length of FFT (fftlen equal to a power of 2), and may also define the…

License : BSD
Language : VHDL

FPGA-Based PID Controller

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License : LGPL
Language : VHDL

Standalone Population Counter Generator

C code for generating a stand-alone population counter with user-defined size (number of input bits) and latency (number of clock cycles) in VHDL.

License : LGPL
Language : C/C++

Priority Encoder - Verilog Parameterized Encoder

Module of parameterized encoder based on verilog. Synthesized to multi-input OR elements. Example of 16 to 4 priority encode: parameter…

License : LGPL
Language : Verilog

Single 14 Segment Display Driver with Limited ASCII Decoder

The module expects ASCII character code (in 8-bit binary) and displays the coresponding character on single digit 14-segment monocolor LED display.…

License : LGPL
Language : VHDL

PYRAMID Algorithm Integer Multiplier Unit

Before You read This is a brief overview of the article about the series of multiplication algorithms. For comparison and estimation of proposed…

Reconfigurable Hardware Platform

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License : LGPL
Language : Other