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Category: All IP Cores (1032)

Data unConfuser Engine

Hi, Everyone, You can find detailed information about project in this pdf. The pdf explains most of the things about the project like: 1. Port list…

License : LGPL
Language : Verilog

Universal Programming Cable

The goal was to create a set of HDL designs that can convert a small PLD to emulate any JTAG/ISP/Download cable. In most cases those designs are…

Language : Verilog

uTosNet Framework - Utilize dual-port BlockRam in the FPGA

The uTosNet framework aims at providing a very fast method for interfacing physical components, such as motor drivers, ADCs, encoders, and similar,…

License : LGPL
Language : VHDL

Veristruct - an IEEE1364.1995 Preprocessor

Overview Veristruct is an an IEEE1364.1995 preprocessor that adds some C-style struct support to the Verilog language. It takes as input Veristruct…

License : LGPL
Language : Verilog

VHDL File-based CPU Emulator

Description of project This project emulates a CPU for an FPGA under simulation with the use of text files. It can be used to test an FPGA - CPU…

License : GPL
Language : VHDL

WB Interface for TI 5x DSP (WB2HPI)

WB Interface for TI 5x DSP (HPI) developed for use with Opencores PCI Bridge. Features 1. Direct access to DSP Control Registers 2. Block transfer…

16-bit Classical CPU Based Loosely on Caxton Foster’s Blue CPU

A 16-bit classical CPU based loosely on Caxton Foster's Blue CPU from the book "Computer Architecture". Includes a cross assembler…

License : LGPL
Language : Verilog

Real Time Clock IP Core with Wishbone Bus Complaint

Real Time Clock IP core with wishbone bus complaint. The RTC can transmit data to CPU as Binary Coded Decimal (BCD) values through wishbone bus.…

AHB Master to WishBone Slave Bridge

A AHB master to WishBone slave bridge along with a basic testbench is included. Burst in not yet supported.

License : LGPL
Language : Verilog

WS2812 RGB LED String Driver

Have you ever wanted to add some color to your project? Then this might be your answer. The WS2812 RGB LED "pixels" and WS2811 driver ICs…

License : LGPL
Language : VHDL

Xilinx Configuration Port (ICAPE2) via Wishbone

As the title says, this core provides access to the Xilinx Internal Configuration Access Port, Edition 2, via a 32-bit wishbone bus. The ICAPE2…

License : GPL
Language : Verilog

16 Bit Microcontroller VHDL Assembler

Features 800 Xilinx slices for CPU 1000 Xililinx slices for complete SoC Optimized for exeution of C programs VHDL, Assembler, C Compiler,…

License : LGPL
Language : VHDL

16-bit Open uRISC Core Processor

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License : LGPL
Language : VHDL

1664 Microprocessor - Simulator Source Configurable

Overview 16,32,64 bit microprocessor - simulator source configurable. 16 bit fixed instruction length. All instructions conditional. up-to 128…

License : Others
Language : C/C++

Simple RISC 32-bit Pipelined Processor

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License : LGPL
Language : Verilog

MC6809/HD6309 Compatible Core Processor

A verilog, vendor independent, no cycle accurate MC6809/HD6309 compatible processor core. Goals: - Execute all implemented opcodes - Allow…

License : LGPL
Language : Verilog

FPGA-Based 6502 Processor in VHDL

Features - feature1 - feature2 Status - ... - ...

A-Z80 CPU - Implementation of the Venerable Zilog Z80 Processor

Update: Rewritten in pure Verilog, the CPU can now be used on both Altera and Xilinx devices! A-Z80 is a conceptual implementation of the venerable…

License : LGPL
Language : Verilog

Cpu Generator - Cpugen (TM) Generates Customizable RISC CPU Cores

Cpugen (TM) generates customizable RISC cpu cores. It allows direct customization of address/data/instruction bus size, interrupt handling,…

Language : VHDL

i650 - Verilog RTL Implementation of the Venerable IBM 650 Computer

A Verilog RTL implementation of the venerable IBM 650 computer. The goal of this project is to use available source materials to recreate a 650 as…

License : LGPL
Language : Verilog