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Category: All IP Cores (1032)

ROSETTA Configurable Dot Matrix Display Controller

ROSETTA Configurable Dot Matrix Display Controller

The ROSETTA Configurable Dot Matrix Display Controller core provides a modular expandable interface for any dimension displays build from LEDs dot…

License : GPL
Language : Other
Macroblock Motion Detection

Macroblock Motion Detection

The 'Macroblock Motion Detection Project' contains modules to perform motion search of macroblocks in the previous video frame for the…

Language : Verilog
ELM Embedded Processor

ELM Embedded Processor

n/a

License : Others
Language : Verilog
FWRISC - Featherweight RISC-V RV32I Implementation

FWRISC - Featherweight RISC-V RV32I Implementation

FWRISC is a Featherweight RISC-V RV32I implementation. All instructions and registers are supported. Source is hosted on GitHub:…

License : Others
Language : Verilog
Fluid Core - A Reconfigurable Pipelined RISC Processor

Fluid Core - A Reconfigurable Pipelined RISC Processor

Fluid Core is a soft core processor aimed at being heavily parameterized in order to support reconfiguration. It has a scalable datapath width i.e.…

License : LGPL
Language : Verilog
FPz8 - Zilog Z8 Encore (eZ8) 8-bit Core Softcore Processor

FPz8 - Zilog Z8 Encore (eZ8) 8-bit Core Softcore Processor

FPz8 is a softcore processor based on Zilog Z8 encore (eZ8) 8-bit core. FPz8 features 2kb of RAM, 16kb of program memory, 8-level vectored…

License : LGPL
Language : VHDL
HC11 Compatible - Gator uProcessor

HC11 Compatible - Gator uProcessor

Gator Microprocessor (GuP) Overview - Motorola/Freescale 68xx Architecture - Source-code and machine-code compatible 68HC11 cpu core - Compatible…

License : LGPL
Language : VHDL
HF-RISC - 32-bit 3-stage Pipelined MIPS / RISC-V Microcontroller

HF-RISC - 32-bit 3-stage Pipelined MIPS / RISC-V Microcontroller

HF-RISC is a small 32-bit, in order, 3-stage pipelined MIPS / RISC-V microcontroller designed at the Embedded Systems Group (GSE) of the Faculty of…

License : GPL
Language : VHDL
K68 - 68k Binary Compatible CRISC Processor

K68 - 68k Binary Compatible CRISC Processor

The k68 is a 68k binary compatible CRISC processor. It supports all twelve (12) addressing modes and most of the instructions for a 68000. It has…

Language : Verilog
HITACHI HD63701 Compatible IP Core Processor

HITACHI HD63701 Compatible IP Core Processor

This project provides a synthesizable IP core compatible with HITACHI HD63701 processors.

License : LGPL
Language : Verilog
HiCoVec - Configurable 32-bit Scalar Unit SIMD CPU

HiCoVec - Configurable 32-bit Scalar Unit SIMD CPU

HiCoVec - a configurable SIMD CPU The HiCoVec processor is based on a simple 32 bit scalar unit and connected with a vector unit for SIMD…

License : GPL
Language : VHDL
MPX 32-bit Processor

MPX 32-bit Processor

n/a

License : LGPL
Language : Verilog
HIVE - a 32-bit General Purpose Soft Processor Core

HIVE - a 32-bit General Purpose Soft Processor Core

Quick link to the design document v08.06: http://www.mediafire.com/view/vp3hb8phe3t5yh4Hive_Design_2015-09-03.pdf Quick link to everything…

License : Others
Language : Verilog
HPC-16 - Simple 16-bit Microprocessor

HPC-16 - Simple 16-bit Microprocessor

Simple 16-bit microprocessor, 16-general purpose registers. custom instruction set, load-store RISC but current implementation "impl0"…

License : LGPL
Language : VHDL
HyperMTA 256 Multithreaded Processor

HyperMTA 256 Multithreaded Processor

HyperMTA is a multithreaded processor capable of having up to 256 threads. In today's super computing/high end world more and more processors…

i8080 Compatible Processor Using Bit-slice Tech and Microcoding

i8080 Compatible Processor Using Bit-slice Tech and Microcoding

Goal: Implement i8080 compatible processor code in VHDL, using bit-slice technology and microcoding. Background: Retro-computing is fun and rich in…

License : LGPL
Language : VHDL
Or1k SoC Altera Embedded Dev Kit for OpenRISC 1200 Implementation

Or1k SoC Altera Embedded Dev Kit for OpenRISC 1200 Implementation

This project is to implement a SoC of using OpenRISC 1200 and many open source IP cores from opencores.org on Nios II Embedded Evaluation Kit…

License : LGPL
Language : Verilog
Ion - MIPS(tm) Compatible CPU

Ion - MIPS(tm) Compatible CPU

WARNING This project is has been canceled after years of neglect. It has been cloned in a new GitHub repository and any further development, if…

License : LGPL
Language : VHDL
JOP: Real-time Enhanced Thread Model Java Optimized Processor

JOP: Real-time Enhanced Thread Model Java Optimized Processor

JOP is the implementation of the Java Virtual Machine (JVM) as concrete machine in hardware. The design has been sucessfully implemented in low…

License : GPL
Language : VHDL
Leros - 16-bit Tiny Microcontroller Optimized for FPGAs

Leros - 16-bit Tiny Microcontroller Optimized for FPGAs

Leros is a 16-bit processor optimized for FPGAs. It consumes less than 200 logic cells and 1-2 on-chip memories. Leros is programmed in assembler…

License : BSD
Language : VHDL