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Category: All IP Cores (1032)

Edge Processor Microarchitecture Implementation for MIPS1 ISA

Edge Processor Microarchitecture Implementation for MIPS1 ISA

Edge is a microarchitecture implementation for mips1 ISA. It has a 32 bit datapath divided into five pipeline stages operating at 50 MHz…

License : LGPL
Language : Verilog
Educational 16-bit MIPS Processor

Educational 16-bit MIPS Processor

This project was aimed at providing people a simple, runnable, and easy-to-enhance MIPS CPU main architecture, along with well commented Verilog…

License : LGPL
Language : Verilog
Educational Implementable RISC Core Processor

Educational Implementable RISC Core Processor

An implementable and enhancable RISC Core developed in Verilog HDL, tested on Xilinx IIE Spartan FPGA. Features - feature1 - feature1.1 -feature1.2…

Language : Verilog
R2000 Soc

R2000 Soc

n/a

License : LGPL
Language : Verilog
Software Aided Wishbone Extension For Xilinx (R) PicoBlaze (TM)

Software Aided Wishbone Extension For Xilinx (R) PicoBlaze (TM)

This project provides interface logic and assembler routines, giving PicoBlaze (TM) embedded soft-uC the ability to access wishbone systems or…

License : BSD
Language : Verilog & VHDL
Sweet32 CPU

Sweet32 CPU

Sweet32 is best described as a ‘no-frills’ Minimal-RISC 32bit microprocessor, created by Valentin Angelovski in Melbourne Australia. Designed…

License : LGPL
Language : VHDL
Wishbone High Performance Z80

Wishbone High Performance Z80

The purpose of the Wishbone Z80 development is to provide a “low-end engine” (written in verilog) that could logically interface with many of…

Language : Verilog
Assembler With VHDL User-defined Commands (AVUC)

Assembler With VHDL User-defined Commands (AVUC)

Here is proposed a method to implement short structured programs inside an FPGA. The novelty of the proposed method resides in that the commands…

License : LGPL
Language : VHDL
EPC RFID Transponder

EPC RFID Transponder

n/a

License : LGPL
Language : VHDL
GECKO4 SoC Co-design Environment

GECKO4 SoC Co-design Environment

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : Others
Language : VHDL
Generic AHB Matrix

Generic AHB Matrix

Generic AHB matrix. It is a multi-master, multi-slave non-blocking AHB matrix with round-robin arbitration. Builds Verilog AHB matrices according…

License : LGPL
Language : Verilog
Generic AXI Interconnect Fabric

Generic AXI Interconnect Fabric

Generic AXI interconnect fabric. It is a multi-master, multi-slave non-blocking AXI fabric with round-robin arbitration. Builds Verilog AXI…

License : LGPL
Language : Verilog
Generic AXI To AHB Bridge

Generic AXI To AHB Bridge

Generic AXI to AHB bridge. Built according to input parameters: AXI command depth, data bits, etc. Supports error on illegal AHB bursts and AHB…

License : LGPL
Language : Verilog
Generic AXI To APB Bridge

Generic AXI To APB Bridge

Generic AXI to APB bridge. Builds design according to required number of slaves, address decoding, AXI command depth, etc. Supports decode error,…

License : LGPL
Language : Verilog
PSS (Programmable Supervisor For Systems-on-Chip)

PSS (Programmable Supervisor For Systems-on-Chip)

PSS (Programmable Supervisor for Systems-on-chip) is a soft IP core that targets to provide the basic means for conducting service operations…

License : BSD
Language : Verilog & VHDL
AHBmaster For FPGA Of Microsemi

AHBmaster For FPGA Of Microsemi

microsemi用のAHBmaster.vhd…

License : LGPL
Language : VHDL
PRBS Signal Generator And Checker

PRBS Signal Generator And Checker

n/a

License : LGPL
Language : Verilog
SystemVerilog Directed Test Bench

SystemVerilog Directed Test Bench

The SystemVerilog Directed Test Bench. This project contains an exact duplication of the VHDL Test Bench Package parser and usage model. This…

License : Others
Language : Other
VHDL Whisbone Test Bench

VHDL Whisbone Test Bench

For the development of IP cores a test bench is needed. The given project provides a test bench written in VHDL which controls the stimulus,the…

License : LGPL
Wishbone Version : B.3
Language : VHDL
AXI4 To VGA Frame Buffer With Linux Driver

AXI4 To VGA Frame Buffer With Linux Driver

This design is very simple in one verilog file. There is 2 version of the design : RGB332 (one pixel is one byte) and RGB565 (one pixel is 2 bytes)…

License : LGPL
Language : Verilog