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This is a behavioral module for parallel scrambler/descrambler. There are RTL scrambler modules available, the purpose of this project is to built…
VHDL implementation of a fast space- and resource-efficient logarithm approximation unit for FPGAs. The unit is an implementation of the ICSILog…
VHDL project for a Square Root Unit (SRU) for 32-bit fixed point data. The unit implements the Goldschmidt recursion algorithm. It is pipelined…
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This project implements the Galois Linear-feedback Shift Register (LFSR) in VHDL, and can be used for applications such as PRBS generation &…
This project is developed at Reconfigurable Computer Laboratory - FRM - UTN, and allows simulate and synthesize the Gregory-Newton extrapolation…
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The lfsr core is a random number generator based on linear feedback shift register(LFSR).The sequence generated has the maximum length possible.The…
the aim of this design to build combinatorial digital circuit to find in fast parallel the maximum or the minimum of set of given set data where…
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QFP32 Arithmetic Core implements a full customizable arithmetic core using the QFP32 format. Available arithmetic operations are easily configured…
Ray Tracing : A rendering technique that challenges anyone who is interested in Computer Science, Computer Graphics and Digital Systems in General.…
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The module expects ASCII character code (in 8-bit binary) and displays the coresponding character on single digit 14-segment monocolor LED display.…
Goal: Implement signed/unsigned 32/16 bit multiplier/divider using a finite state machine (and use it for a fun project) Background: I needed a…
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The DLX processor is an academic processor described in in John L. Hennessy and David A. Patterson's Computer Architecture: A Quantitative…
A custom instruction for approximation of the hyperbolic tangent function tanh(x) with a max. error of 0.1
CORDIC is the acronym for COordinate Rotation DIgital Computer and allows a hardware efficient calculation of various functions like - atan, sin,…
This PRNG uses Fibonacci LFSRs with a estimated period of 3.40282366920938463463374607431768211455 × 10^38 clock cycles Expression: X^128 + X^126…
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