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Introduction The aim of the OpenRISC project is to create a free, open source computing platform available under the GNU (L)GPL license. Platform…
AltOR32 is an OpenRISC 1000 architecture derived RISC CPU targeted at small FPGAs and contains only the most basic ISA features from the OpenRisc…
A 16-bit classical CPU based loosely on Caxton Foster's Blue CPU from the book "Computer Architecture". Includes a cross assembler…
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A verilog, vendor independent, no cycle accurate MC6809/HD6309 compatible processor core. Goals: - Execute all implemented opcodes - Allow…
Update: Rewritten in pure Verilog, the CPU can now be used on both Altera and Xilinx devices! A-Z80 is a conceptual implementation of the venerable…
A Verilog RTL implementation of the venerable IBM 650 computer. The goal of this project is to use available source materials to recreate a 650 as…
UPDATE 1-Jan-2014: This project has moved to GitHub. Please visit https://github.com/granteamips32r1 for the latest code. No further changes will…
The AE18 is a clean room implementation of the Microchip PIC18 series CPU core using information from the PIC18C documentation from their website.…
The aeMB is a clean room implementation of the EDK3.2 compatible Microblaze core using information from the Internet. It is cycle and instruction…
This project is based on MIPS789 opencores project.We used MIPS789 core and added the cache infrastracture and AMBA bus from LEON3.The final core…
The Amber processor core is an ARM-compatible 32-bit RISC processor. The Amber core is fully compatible with the ARM® v2a instruction set…
Other project properties Category:Processor Language:Verilog & VHDL Development status:Alpha Additional info: WishBone compliant: No WishBone…
This is a configurable Atmel processor and support eight configurations: 1) REDUCED 2) MINIMAL 3) CLASSIC_8K 4) CLASSIC_128K 5) ENHANCED_8K 6)…
Brainfuck CPU is a hardware implementation of Brainfuck programing language. It uses simple 2-stage pipelining and Harvard's architecture. This…
Edge is a microarchitecture implementation for mips1 ISA. It has a 32 bit datapath divided into five pipeline stages operating at 50 MHz…
This project was aimed at providing people a simple, runnable, and easy-to-enhance MIPS CPU main architecture, along with well commented Verilog…
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Fluid Core is a soft core processor aimed at being heavily parameterized in order to support reconfiguration. It has a scalable datapath width i.e.…
This project provides a synthesizable IP core compatible with HITACHI HD63701 processors.
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