This core implements Forward and Inverse Discrete Wavelet Transform (FDWT and IDWT) on still image. Wavelet LeGall 5/3 is selected in design. The…
G.729A codec core performs encoding and decoding of 16-bit LPCM audio samples according to ITU-T G.729A standard. The codec core supports multiple…
CVS is currently out of date, update when I get the time (as well as things such as schematics) Custom built and designed video game system. Also…
IP Core for FPGA Configuration Controller from MMC Card. Can configure an FPGA in serial mode from continous blocks stored on MMC Card. Smallest…
This project is to design a Fuzzy Logic Hardware Accelerator (FLHA) that is WishBone compatible. FLHA is capable of generating fuzzy rule matrix…
Please write a description of the project here. It is used as a MetaTag (search engines looks at this).
Benefits of data compression The use of lossless data compression can bring about a number of increasingly important benefits to an electronic…
n/a
Vectorial generator: -Interface: bit or bus -Configuration: dynamic -Applications: waveform generator, serial or parallel communication Examples:…
GroundHog 2009 is a benchmark suite for reconfigurable architectures in the mobile domain. The benchmark suite can be downloaded from…
Debug Interface is used for development purposes (debugging). It is an interface between the CPU(s), peripheral cores and any commercial…
Hardware looping unit Tha main purpose of the hardware looping unit (HWLU) is to enhance program control units found in modern microprocessors, by…
This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The…
Please write a description of the project here. It is used as a MetaTag (search engines looks at this).
This implementation of the Test Access Port (TAP) is fully IEEE 1149.1 compliant. It includes a TAP controller, a 4-bit instruction register and…
The controller scans the keyboard by making a different column in "rows" logic-0 therefor the inputs "cols" have to be PULL-UP…
LFSR Counter Generator is a command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The…
This is an experimental oscilloscope VHDL design working on the Xilinx Spartan-3E starter board. The analog signal is sampled with a TI ADC08200…
Have you ever wanted to add some color to your project? Then this might be your answer. The LPD8806 RGB LED strings are available for low cost from…
The aim of the project is to develop oscilloscope functions (conversion control, trigger, FFT, ...) in several cores and implement a usefull…