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Category: All IP Cores (1032)

16x2 LCD controller for Xilinx

16x2 LCD controller for Xilinx

Controller for 16 character - 2 line LCD displays as used on various Xilinx evaluation boards. Features - 4-bit LCD data interface - One…

License : LGPL
Language : VHDL
2nd order Sigma-Delta DAC

2nd order Sigma-Delta DAC

Public domain code of the 2nd order Sigma-Delta DAC. Allows to produce reasonable quality audio signal from single digital ouput pin in the FPGA.…

License : Others
Language : VHDL
An Alternative Oscilloscope (AlternaScope)

An Alternative Oscilloscope (AlternaScope)

AlternaScope provides a cheap alternative to expensive oscilloscopes; Using a VGA display and a simple mouse interface, a user can use this scope…

Language : Verilog
VHDL 6532 RIOT (RAM-I/O-TIMER)

VHDL 6532 RIOT (RAM-I/O-TIMER)

VHDL implementation of the 6532 RIOT (RAM-I/O-TIMER) Like the original chip from Mostek/Rockwell, this component is 6500/6800 bus compatible. The…

License : Others
Language : VHDL
Artificial Intelligence System Using FGPA/ASIC

Artificial Intelligence System Using FGPA/ASIC

The Artificial Intelligence System is a neuromorphic FPGA/ASIC project undertaken by a number of volunteers with the scope of simulating real-time…

License : Others
Language : VHDL
Adjustable Frequency Divider

Adjustable Frequency Divider

Usage and Operation In order to operate the circuit correctly it must first be reset (asynchronously). Below is a timing diagram that illustrates…

License : LGPL
Language : Verilog
Programmable Sound Generator AY-3-8910 Compatible Module

Programmable Sound Generator AY-3-8910 Compatible Module

This module is software compatible with the PSG (Programmable Sound Generator) AY-3-8910. It can be used to produce music.

License : GPL
Language : Verilog
Avalon to Wishbone Bridge

Avalon to Wishbone Bridge

AVALON/WISHBONE Bridge This is an Avalon to WishBone Bridge. Avalon is a bus standard mainly used in Altera(Now Intel) Tools. Wishbone as every one…

License : LGPL
Wishbone Version : B.4
Language : Verilog
Simple backtracking 9x9 Sudoku Solver in Verilog

Simple backtracking 9x9 Sudoku Solver in Verilog

Simple backtracking 9x9 Sudoku solver written in Verilog. Uses an exact cover algorithm to quickly find a solution with minimal backtracking (C…

License : BSD
Language : Verilog
BU PACMAN Game with Advanced Digital Design Using Verilog

BU PACMAN Game with Advanced Digital Design Using Verilog

This is for the final project of EC551 Advanced Digital Design using Verilog, a course offered in Boston University. It's basically the classic…

License : GPL
Language : Verilog
BigCounter for Xilinx FGPA

BigCounter for Xilinx FGPA

Uses the shift register technology to create a big counter, that gives out a pulse at the period specified as a generic Features Designed for…

License : GPL
Language : VHDL
Boundaries: Glitch-free Clock Switch Circuit

Boundaries: Glitch-free Clock Switch Circuit

This project is a collection of small designs involved with clock boundaries. The clock_switch designs are based on an eetimes article. The…

Language : Verilog
Computer Operating Properly : Watchdog Timer Module

Computer Operating Properly : Watchdog Timer Module

The Computer Operating Properly Module, COP, is a watchdog timer module that triggers a system reset if it is not regularly serviced by writing two…

License : BSD
Language : Verilog
Open Source FPGA Bitcoin Miner for Altera and Xilinx

Open Source FPGA Bitcoin Miner for Altera and Xilinx

n/a

License : LGPL
Language : VHDL
FGPA Connect6 Solver

FGPA Connect6 Solver

CONNECT-6 SOLVER Connect-6 is usually played on a 19 × 19 GO Board, with each player having either black or white pieces. The Black starts…

License : GPL
Language : C/C++
Bubble Sort Module in Verilog

Bubble Sort Module in Verilog

simple fast bubble sort module in verilog

License : LGPL
Language : Verilog
RFC 1951 - DEFLATE Data Compression Algorithm

RFC 1951 - DEFLATE Data Compression Algorithm

A VHDL implementation of the open DEFLATE data compression algorithm. The DEFLATE standard is specified in RFC 1951 and was jointly developed by…

License : GPL
Language : VHDL
DNA Sequence Alignment Accelerator

DNA Sequence Alignment Accelerator

This is an easily configurable systolic array of processors to compute the optimal alignment between two DNA sequences. It supports affine gap…

License : LGPL
Language : Verilog
First File Reader on FAT16 File System

First File Reader on FAT16 File System

The aim of this Core is to track the first file saved into a FAT16 volume and to read the information from it offering those data to a Wishbone bus…

Language : VHDL
Cray-2-Reboot for FPGAs

Cray-2-Reboot for FPGAs

Files also located at: https://github.com/DarkwaveTechnologiesCray-2-Reboot The goal of this project is to make a clock and gate equivalent…

License : LGPL
Language : Verilog