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Category: All IP Cores (1032)

Wormhole Routing Network-on-Chip - NoC Simulator

Wormhole Routing Network-on-Chip - NoC Simulator

NoC(Network-on-Chip) Features -Maximum 4 by 4 Tiles -The synchronizing FIFO -Wormhole routing -Virtual channel(3 stage buffer) -User reconfigure…

License : LGPL
Language : SystemC
4-way set associative Next186MP3 Decoder

4-way set associative Next186MP3 Decoder

This is an evolution of my previous project, Next186SoC PC, able to play MP3 files in real time (any bitrate). It is written in Verilog, and it…

License : LGPL
Language : Verilog
OC - H.264 Encoder SoC Solution Based on Open-source Blocks

OC - H.264 Encoder SoC Solution Based on Open-source Blocks

The goal is to develop an H.264 Encoder SoC (System-on-Chip) solution based only on open-source blocks. Status 2009-08-24: A software-team is…

License : LGPL
Language : Verilog
NoCem - Synthesizable VHDL Network on Chip Emulator

NoCem - Synthesizable VHDL Network on Chip Emulator

A Network on Chip Emulation Tool, NoCem is a body of VHDL code configurable by a toplevel package file that can create a variety of Network on…

License : GPL
Language : VHDL
Martins SoC Instancing, Simulation Toolchain Builder

Martins SoC Instancing, Simulation Toolchain Builder

The MaSoCist is an acronym for 'Martins SoC Instancing, Simulation Toolchain'. It is a VHDL collection and toolchain based on various open…

License : Others
Wishbone Version : B.3
Language : VHDL
OMS8051 MINI - Open 8051 Based Embedded System

OMS8051 MINI - Open 8051 Based Embedded System

Is a Open 8051 based Embededed System, Include a 8051 with Following SubSystem 32K Program Memory 32K Data Memory 1x I2C Master 1x I2C Slave 1x SPI…

License : LGPL
Language : Verilog
NoCmodel - Python Module for Network-on-Chip Modeling

NoCmodel - Python Module for Network-on-Chip Modeling

NoCmodel is a Python module for Network-on-Chip modeling, with add-ons for simulation (functional or RTL) and code generation (initially VHDL).…

License : LGPL
Language : Other
SardMIPS - Synthesizable Parametric IP Core of 32-bit RISC Processor

SardMIPS - Synthesizable Parametric IP Core of 32-bit RISC Processor

Embedded MIPS R2000 It's a synthesizable parametric IP core of 32 bit RISC processor supporting full MIPS R2000 ISA, by using SystemC HDL. An…

License : GPL
Language : Other
PCIe Scatter-Gather DMA Engine controller for Virtex5 and Virtex6

PCIe Scatter-Gather DMA Engine controller for Virtex5 and Virtex6

Overview This package involves a PCIe Scatter-Gather DMA engine for Virtex5 and Virtex6. The design implements MAC, Physical (Xilinx Hard and Soft…

License : LGPL
Language : VHDL
32-bit RISC OpenFire Soft Processor on DLX architecture

32-bit RISC OpenFire Soft Processor on DLX architecture

The OpenFire soft processor is an open source Verilog implementation of the Xilinx MicroBlaze. Like the MicroBlaze, the OpenFire is a 32-bit RISC…

Language : Verilog
OpenSPARC-based SoC on Linux/OpenSolaris

OpenSPARC-based SoC on Linux/OpenSolaris

OpenSPARC-based SoC is a project aimed to create a SoC based on OpenSPARC cores (T1 and T2) with OpenCores and other open-source peripherals added,…

License : GPL
Language : Verilog
OpenRISC 1200 SOC on Terasic DE1

OpenRISC 1200 SOC on Terasic DE1

Overview This project is an example of using OpenRISC on an Terasic DE1 development board. UBoot has been ported. The old ecos 2.0 has been ported…

Language : Verilog
EziDebug - Easy-to-use Versatile Logic Simulation Tool

EziDebug - Easy-to-use Versatile Logic Simulation Tool

EziDebug is an easy-to-use versatile logic simulation tool for verification and debugging of digital circuits. It supports inserting scan chains in…

License : LGPL
Language : C/C++
Programmed Data Processor-1 (PDP-1) Reimplementation Using FPGA

Programmed Data Processor-1 (PDP-1) Reimplementation Using FPGA

PDP-1 reimplementation using an FPGA. The goal is to run old software like Spacewar!, the music compiler, and Expensive Typewriter on current FPGA…

License : LGPL
Language : VHDL
Fully Synthesizable Tensilica PIF2WB IP Core Bridge

Fully Synthesizable Tensilica PIF2WB IP Core Bridge

This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as…

Language : VHDL
32-bit interface CoreConnect PLBv46 to Wishbone Bridge

32-bit interface CoreConnect PLBv46 to Wishbone Bridge

PLBv46 to Wishbone Bridge This is a simple CoreConnect PLBv46 to Wishbone bridge that can allow Wishbone peripherals to be used on Xilinx processor…

Language : VHDL
Modified Project Oberon for SDRAM and DDRAM Interface

Modified Project Oberon for SDRAM and DDRAM Interface

Project Oberon http://www.projectoberon.com modified to use SDRAM instead of static RAM Static RAM is old technology in FPGA world, and 1MB 32bit…

License : LGPL
Language : Verilog
Real-time Image Component Labeling and Feature Extraction

Real-time Image Component Labeling and Feature Extraction

INFO The project is RT level design of image component labeling and feature extraction. The design is captured in VHDL. The architecture is…

License : LGPL
Language : VHDL
Stephen Weis RFID Tag and Reader

Stephen Weis RFID Tag and Reader

Features - hash lock - blinded anticollision Status - implemented Stephen Weis RFID tag model http://theory.lcs.mit.edu/~cis/thesesweis-masters.pdf…

License : GPL
Language : Verilog
RTF68k System-on-Chip (SOC) Using Wishbone Bus Interface

RTF68k System-on-Chip (SOC) Using Wishbone Bus Interface

This is a complete system-on-a-chip. Developed on a Diligent Spartan3e board, the SOC includes CPU (TG68), bitmap and text displays, PSG, keyboard…

License : LGPL
Language : Verilog & VHDL