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Category: All IP Cores (1032)

Soft Multiprocessor Architecture on FPGA

Soft Multiprocessor Architecture on FPGA

Soft Multiprocessor on FPGA is becoming more attractive as the design cost and NRE soaring up in deep-submicron age, especially for high…

License : GPL
Language : VHDL
SimpCon - a Simple and Efficient SoC on-chip Interconnect

SimpCon - a Simple and Efficient SoC on-chip Interconnect

SimpCon is a specification for a simple and efficient system-on-chip (SoC) interconnect. SimpCon provides single cycle commands and provisions for…

License : LGPL
Simple AXI4-Lite bridges for IPbus and Wishbone

Simple AXI4-Lite bridges for IPbus and Wishbone

This project provides very simple bridges from AXI4-Lite interface to IPbus and Wishbone buses. The design has been tested on Xilinx Zynq (Z-Turn…

License : Others
Language : VHDL
STORM SoC (System on Chip) with 32-bit Wishbone Bus System

STORM SoC (System on Chip) with 32-bit Wishbone Bus System

Welcome to the STORM SoC project! This is an FPGA/evaluation board-independent, complete system on chip implementation based on the STORM CORE…

License : GPL
Language : VHDL
SBA - Simple Bus Architecture System Creator

SBA - Simple Bus Architecture System Creator

The Simple Bus Architecture (SBA) is an architecture made up software tools and intellectual property cores (IP Cores) interconnected by buses set…

License : LGPL
Language : VHDL
High Speed Data rate System-on-Chip Wire (SoCWire)

High Speed Data rate System-on-Chip Wire (SoCWire)

System-on-Chip Wire (SoCWire) SoCWire has been developed by IDA, Technical University Braunschweig. It is a Network-on-Chip (NoC) approach based on…

Language : VHDL
WISHBONE Builder - Wishbone Interconnect Matrix Generator

WISHBONE Builder - Wishbone Interconnect Matrix Generator

The intention is to provide an easy way to create and change a system based on the WISHBONE bus. The user shall be able to try different…

Language : Verilog
System05 - VHDL 6805 Compatible Core

System05 - VHDL 6805 Compatible Core

6805 compatible CPU Core. Does not have any of the standard 6805 on chip peripherals at this stage other than the parallel I/O port. This was the…

License : GPL
Language : VHDL
WISHBONE to OPB Bus Interface Wrappers

WISHBONE to OPB Bus Interface Wrappers

OPB ->WISHBONE and WISHBONE->OPB bus interface wrappers OPB Bus to WISHBONE bus and WISHBONE bus to OPB bus interface wrappers. The Interface…

Language : Other
WISHBONE Protocol to AHB Protocol Bridge

WISHBONE Protocol to AHB Protocol Bridge

Features - AHB 2.0 compliant - Wishbone B.3 compliant - WISHBONE Burst NOT SUPPORTED - Fully synthesisable - Synchronous - Verilog RTL - Includes a…

Language : Verilog
WISHBONE Interconnect Matrix IP Core

WISHBONE Interconnect Matrix IP Core

This is a WISHBONE Interconnect Matrix IP core.It can interconnect up to 8 Masters and 16 Slaves Some of the main features are: - Up to 8 Masters -…

Language : Verilog
WISHBONE Interconnect ShareBus IP Core

WISHBONE Interconnect ShareBus IP Core

This is a WISHBONE Interconnect ShareBus IP core.It can interconnect up to 8 Masters and 8 Slaves Some of the main features are: Up to 8 Masters Up…

WISHBONE DMA/Bridge IP Core with up to 8 Priority Levels

WISHBONE DMA/Bridge IP Core with up to 8 Priority Levels

This is a simple DMA/Bridge IP core. It has two WISHBONE interface. It can perform DMA transfers between the two interfaces or on the same…

Language : Verilog
PlTbUtils for Automatic, Self-checking Simulation Testbenches

PlTbUtils for Automatic, Self-checking Simulation Testbenches

PlTbUtils makes it easy to create automatic, self-checking simulation testbenches, and to locate bugs during a simulation. It is a collection of…

License : LGPL
Language : VHDL
JPEG/MJPEG Decoder on a Virtex-II Pro FPGA at 100 MHz

JPEG/MJPEG Decoder on a Virtex-II Pro FPGA at 100 MHz

A hardware based system to decode JPEG baseline compressed image data. The different stages of the decoding process are implemented in a pipelined…

License : GPL
Language : VHDL
Simulated and Synthesized Wishbone Out Port From B3 Spec

Simulated and Synthesized Wishbone Out Port From B3 Spec

Are you using Wishbone, do you need some simple 'slaves' to test your bus with ? Well, the Wishbone spec, appendix B3, has VHDL examples of…

License : LGPL
Language : VHDL
Wishbone SoC for Motorola 6800/01 CPU Based Project

Wishbone SoC for Motorola 6800/01 CPU Based Project

A Wishbone SoC of a 6800/01 CPU based project Features - Motorola 6800/01 'instruction set' CPU CORE (Object code compatable) - RMCA01 -…

Language : VHDL
WishboneTK toolkit IP Cores

WishboneTK toolkit IP Cores

WhisboneTK is a set of IP cores designed to be compatible with the Wishbone bus specification. The members of the tool-kit are general purpose…

XuLA2-LX25 SoC System on a Chip Implementation Controller

XuLA2-LX25 SoC System on a Chip Implementation Controller

This project attempts to take two separate projects, the OpenCores ZipCPU and Xess.com's XuLA2-LX25, and merge them together into a single…

License : GPL
Wishbone Version : B.4
Language : Verilog
OpenArty - Implementing ZipCPU on an Arty platform

OpenArty - Implementing ZipCPU on an Arty platform

The purpose of the OpenArty project is to implement a ZipCPU on an Arty platform, together with open source drivers for all of the Arty…

License : GPL
Wishbone Version : B.4
Language : Verilog