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Category: All IP Cores (1032)

Synchronous-DRAM Controller for Intel Microcontroller and x86 Processors

Synchronous-DRAM Controller for Intel Microcontroller and x86 Processors

The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly…

WB LCD character display controller with Wishbone Interfaces

WB LCD character display controller with Wishbone Interfaces

Overview LCD character display controller with Wishbone and memory mapped interfaces. It is compatible with the following parts: Sitronix ST7066U,…

License : LGPL
Language : Verilog
Boost Converter in Verilog

Boost Converter in Verilog

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog
CPU-to-FPGA Bus Transaction Monitor with JTAG

CPU-to-FPGA Bus Transaction Monitor with JTAG

A CPU-to-FPGA bus transaction monitor, captures the CPU write/read address/data to/from memory-mapped registers that resides in the FPGA, and…

License : LGPL
Language : Verilog
DS1621 Verilog Model with Testing Tasks

DS1621 Verilog Model with Testing Tasks

DS1621 verilog model with testing tasks. Testing elements assume the existence of the low level write/read (need to be written by the user) and…

License : LGPL
Language : Verilog
Field-Programmable Oscilloscope (FPO) Logic Analyzer

Field-Programmable Oscilloscope (FPO) Logic Analyzer

This is FPgaOscilloscope or Field-Programmable Oscilloscope FPO resides in FPGA along with the main project and allow to observe their signals.…

License : GPL
Language : VHDL
FROM and TO VHDL files

FROM and TO VHDL files

For make stimulus of testbench some times need work with files from VHDL. I think that will be very good if some different stimulus will be in one…

License : LGPL
Language : VHDL
c - VHDL Co-Simulation with FLI for Simulator Control

c - VHDL Co-Simulation with FLI for Simulator Control

Using ModelSim Foreign Language Interface for c - VHDL Co-Simulation and for Simulator Control on Linux x86 Platform Writing testbenches in VHDL…

License : Others
Language : VHDL
Generic AHB Master Stub for 32/64 data bits, AHB Bursts and Random Wait-states

Generic AHB Master Stub for 32/64 data bits, AHB Bursts and Random Wait-states

Generic AHB master stub. Built out of an AXI master and an AXI2AHB bridge. Supports 32/64 data bits, AHB bursts and random wait-states. The design…

License : LGPL
Language : Verilog
Generic AHB Slave Stub for 32/64 data bits, AHB Bursts and Random Wait-states

Generic AHB Slave Stub for 32/64 data bits, AHB Bursts and Random Wait-states

Generic AHB slave stub. Supports 32/64 data bits, AHB bursts and random wait-states. The design is built according to input parameters: address…

License : LGPL
Language : Verilog
Generic APB Master Stub for APB and APB3 Protocols

Generic APB Master Stub for APB and APB3 Protocols

Generic APB master stub. Based on an AXI master stub and an AXI2APB bridge. Supports both APB and APB3 protocols (APB3 is with pready and pslverr…

License : LGPL
Language : Verilog
Generic AXI Slave Stub for 32/64 data bits, AXI Bursts and Random Wait-states

Generic AXI Slave Stub for 32/64 data bits, AXI Bursts and Random Wait-states

Generic AXI slave stub. Supports 32/64 data bits, AXI bursts and random wait-states. The design is built according to input parameters: address…

License : LGPL
Language : Verilog
Generic APB Slave Stub for APB and APB3 Protocols

Generic APB Slave Stub for APB and APB3 Protocols

Generic APB slave stub. Support both APB and APB3 protocols (APB3 is with pready and pslverr). Supports slave error, random and fixed wait-states.…

License : LGPL
Language : Verilog
Generic AXI Master Stub for Multiple AXI IDs, 32/64 data bits, AXI bursts and random wait-states

Generic AXI Master Stub for Multiple AXI IDs, 32/64 data bits, AXI bursts and random wait-states

Generic AXI master stub. Supports multiple internal masters (multiple AXI IDs), 32/64 data bits, AXI bursts and random wait-states. The design is…

License : LGPL
Language : Verilog
HASM TestBench Vector Generator for FPGA/CPLD designs verification

HASM TestBench Vector Generator for FPGA/CPLD designs verification

HASM Description HASM is a simple instruction simulator for use in the verification of FPGA/CPLD designs that must attach to a processor bus. HASM…

License : LGPL
Language : VHDL
Standalone Minimalist i2clcd IP Core

Standalone Minimalist i2clcd IP Core

i2clcd is a minimalist i2clcd IP core that provides the basic framework for the implementation of custom i2clcd devices. The core provides a means…

License : LGPL
Language : Verilog
Logic Probe - Simple Logic Analyzer

Logic Probe - Simple Logic Analyzer

LogicProbe is a very simple logic analyzer which can be run on an FPGA in parallel with the "device under test". The analyzer has a width…

License : BSD
Language : Verilog
JPEG Encoder Using Baseline Encoding Method

JPEG Encoder Using Baseline Encoding Method

Features • JPEG baseline encoding JPEG ITU-T T.81 | ISO/IEC 10918-1 • Standard JFIF header v 1.01 automatic generation • Color…

License : Others
Language : VHDL
JTAG Chains with JAM STAPL Player

JTAG Chains with JAM STAPL Player

Converts Raspberry Pi into a JTAG programmer (STAPL protocol). Supports two JTAG chains through 26-pin RPi GPIO P1 connector. The TCK rate is…

License : LGPL
Language : C/C++
VHDL Test Bench for FPGA/ASIC Verification

VHDL Test Bench for FPGA/ASIC Verification

Overview The VHDL test bench is a collection of VHDL procedures and functions which allow the user to create their own scripting instructions for…

License : BSD
Language : VHDL