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Generic AHB matrix. It is a multi-master, multi-slave non-blocking AHB matrix with round-robin arbitration. Builds Verilog AHB matrices according…
Generic AXI interconnect fabric. It is a multi-master, multi-slave non-blocking AXI fabric with round-robin arbitration. Builds Verilog AXI…
Generic AXI to AHB bridge. Built according to input parameters: AXI command depth, data bits, etc. Supports error on illegal AHB bursts and AHB…
Generic AXI to APB bridge. Builds design according to required number of slaves, address decoding, AXI command depth, etc. Supports decode error,…
PSS (Programmable Supervisor for Systems-on-chip) is a soft IP core that targets to provide the basic means for conducting service operations…
This project is to implement a SoC of using OpenRISC 1200 and many open source IP cores from opencores.org on Nios II Embedded Evaluation Kit…
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks Version: 0.2 On-chip networks or networks-on-chip (NoCs) are the on-chip…
The ECO32 system is a microprocessor system-on-chip, consisting of a 32-bit CPU and several controllers for peripheral devices (keyboard, character…
AHB Protocol to Wishbone Protocol Bridge. Features - AHB 2.0 compliant - Wishbone B.3 compliant - AHB Burst NOT SUPPORTED - Fully synthesisable -…
Single channel 32 or 64 bit AHB master DMA core. Supports simultaneous read and write, command lists, peripheral control, timeouts and endianess…
The Minimal OpenRISC System on Chip is a system on chip (SoC) implementation with standard IP cores available at OpenCores. This implementation…
The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is…
Single channel 32 or 64 bit AXI master DMA core. Supports simultaneous read and write, outstanding AXI commands, command lists, peripheral control,…
This CMOD-S6 SoC grew out of the desire to demonstrate that a useful ZipCPU soft core implementation could be made in a very small space. In…
Generic APB register file generator. Creates Verilog source, C header file and HTML documentation, from an Excel worksheet. The source files are…
Project Summary Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC…
Description Implements Dense ANN that can directly use the weights from Keras. Still need to add SoftMax, MaxPooling, Conv2D & LSTM The url of…
This project demonstrates the use of the P16C5x soft-processor core, found elsewhere on opencores.org, in a system-on-chip. The project targets a…
PC AT SoC based on Next186 core. CPU runs at up to 80 MHz (80 MIPS), up to 64MB of RAM, HMA available. Able to run DOS6.22, FreeDos, Windows3.0,…
This is an evolution of my previous project, Next186SoC PC, able to play MP3 files in real time (any bitrate). It is written in Verilog, and it…
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