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This application parses a Verilog define file and presents a GUI to the user
Description of project.. Features - feature1 - feature1.1 -feature1.2 -feature2
A platform for execute simple games, with graphics in two dimensions, implemented on Altera DE2-115 development board. • Compatible with Sega…
The Advanced Debug Interface is a suite of IP cores and software programs designed to allow a developer to download code to a target CPU in a…
About this core This is a collection of commonly used base functions, used in all of ASTRONs other cores. These source files can work in any…
Controller for 16 character - 2 line LCD displays as used on various Xilinx evaluation boards. Features - 4-bit LCD data interface - One…
Usage and Operation In order to operate the circuit correctly it must first be reset (asynchronously). Below is a timing diagram that illustrates…
This module is software compatible with the PSG (Programmable Sound Generator) AY-3-8910. It can be used to produce music.
AVALON/WISHBONE Bridge This is an Avalon to WishBone Bridge. Avalon is a bus standard mainly used in Altera(Now Intel) Tools. Wishbone as every one…
This is for the final project of EC551 Advanced Digital Design using Verilog, a course offered in Boston University. It's basically the classic…
Uses the shift register technology to create a big counter, that gives out a pulse at the period specified as a generic Features Designed for…
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CONNECT-6 SOLVER Connect-6 is usually played on a 19 × 19 GO Board, with each player having either black or white pieces. The Black starts…
simple fast bubble sort module in verilog
A VHDL implementation of the open DEFLATE data compression algorithm. The DEFLATE standard is specified in RFC 1951 and was jointly developed by…
This is an easily configurable systolic array of processors to compute the optimal alignment between two DNA sequences. It supports affine gap…
Files also located at: https://github.com/DarkwaveTechnologiesCray-2-Reboot The goal of this project is to make a clock and gate equivalent…
G.729A codec core performs encoding and decoding of 16-bit LPCM audio samples according to ITU-T G.729A standard. The codec core supports multiple…
This project is to design a Fuzzy Logic Hardware Accelerator (FLHA) that is WishBone compatible. FLHA is capable of generating fuzzy rule matrix…
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