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Huffman code is used in the most streaming applications. I have written a Huffman decoder for jpeg pictures. For audio or other data streams the…
This IP core provides resource efficient ternary adders, i.e., adders with three inputs performing s = x + y + z, for the Altera and Xilinx…
kvcordic is a collection of files comprising an implementation of a universal CORDIC algorithm (rotation/vectoring direction,…
This project implements the simple and light protocol for transmission of data from low resources FPGA connected to the Ethernet PHY and an…
The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style…
Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART…
WishboneAXI This project is a universal, configurable Wishbone AXI bridge together with Xilinx IP wrapper, which makes it suitable for Block Design…
Overview IOTA PoW needs a lot of computational power which makes sending transactions on smaller microcontrollers (like ARM) very slow. This is a…
This project comprises the VHDL description and configuration script of a configurable IIR filter. The VIIRF can implement any transfer function…
Public domain code of the 2nd order Sigma-Delta DAC. Allows to produce reasonable quality audio signal from single digital ouput pin in the FPGA.…
VHDL implementation of the 6532 RIOT (RAM-I/O-TIMER) Like the original chip from Mostek/Rockwell, this component is 6500/6800 bus compatible. The…
The Artificial Intelligence System is a neuromorphic FPGA/ASIC project undertaken by a number of volunteers with the scope of simulating real-time…
Vectorial generator: -Interface: bit or bus -Configuration: dynamic -Applications: waveform generator, serial or parallel communication Examples:…
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LXP32 is a lightweight, open source and FPGA-friendly 32-bit CPU IP core. It uses a simple, original instruction set designed for straightforward…
This project is based on an implementation of MIPS I specified core by Steve Rhoads: plasma Interface entity plasma is generic( core_idx : natural…
The Plasma CPU is a small synthesizable 32-bit RISC microprocessor. It is currently running a live web server with an interrupt controller, UART,…
The tinyVLIW8 is a 8-bit soft-core processor for deeply embedded control task. The design is fully implemented in VHDL and tested on the Altera DK1…
The GECKO system is a general purpose hardware/software co-design environment for real-time information processing and/or system-on-chip (SoC)…
Software Defined Radio RX/TX. Consultative Committee for Space Data System (CCSDS) specifications compliant. This is part of a larger project…
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