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Elliptic Curve Group Core

Elliptic Curve Group Core

The Elliptic Curve Group core is for computing the addition of two elements in the elliptic curve group, and the addition of $c$ identical elements…

License : LGPL
Language : Verilog
Fixed Point Arithmetic Modules Verilog

Fixed Point Arithmetic Modules Verilog

This project was started in order to create fixed point (Q format) arithmetic modules in verilog. What was created was a parameterized (specify…

License : LGPL
Language : Verilog
Efficient Floating Point Logarithm Unit for FPGAs

Efficient Floating Point Logarithm Unit for FPGAs

VHDL implementation of a fast space- and resource-efficient logarithm approximation unit for FPGAs. The unit is an implementation of the ICSILog…

License : LGPL
Language : VHDL
32-bit Fixed Point Square Root (Recursive Algorithm)

32-bit Fixed Point Square Root (Recursive Algorithm)

VHDL project for a Square Root Unit (SRU) for 32-bit fixed point data. The unit implements the Goldschmidt recursion algorithm. It is pipelined…

License : LGPL
Language : VHDL
Floating Point Adder and Multiplier

Floating Point Adder and Multiplier

This Floating Point units were developed as part of the HAVOC project. The Design schematics and related files can be browsed at the FPU…

Language : VHDL
Gaussian Noise Generator for FPGAs

Gaussian Noise Generator for FPGAs

The Gaussian Noise Generator core generates white Gaussian noise of standard normal distribution, which can be used to measure BER to extremely low…

License : LGPL
Language : Verilog
FPGA-based Median Filter Architecture

FPGA-based Median Filter Architecture

This implementation project proposes a practical implementation of a Median Filter architecture focused in low-cost FPGA devices. The architecture…

License : LGPL
Language : Verilog
32-bit Floating Point Unit (FPU)

32-bit Floating Point Unit (FPU)

This is a 32-bit floating point unit (FPU), which I developed in a project within the Vienna University of Technology. It can do arithmetic…

Language : VHDL
Hardware Load Balancer for Multi-Stage Software Router

Hardware Load Balancer for Multi-Stage Software Router

n/a

License : LGPL
Language : VHDL
IEEE-754 Compliant FPU Double VHDL

IEEE-754 Compliant FPU Double VHDL

IEEE-754 compliant double-precision floating point unit. 4 operations (addition, subtraction, multiplication, division) are supported, as are the 4…

Language : VHDL
MESI Coherency InterSection Controller

MESI Coherency InterSection Controller

The MESI InterSection Controller (ISC) is a coherence system controller. It supports the MESI coherence protocol for a cache data consistency. It…

License : LGPL
Language : Verilog
Generic Galois LFSR in VHDL

Generic Galois LFSR in VHDL

This project implements the Galois Linear-feedback Shift Register (LFSR) in VHDL, and can be used for applications such as PRBS generation &…

License : LGPL
Language : VHDL
LZRW1 Lossless Data Compressor Core

LZRW1 Lossless Data Compressor Core

This IP core allows lossless data compression based on the Lempel-Ziv-Ross-Williams-1 algorithm. Its focus is on high throughput (of uncompressed…

License : GPL
Language : VHDL
Generic Galois LFSR Generator in MyHDL

Generic Galois LFSR Generator in MyHDL

An n-width Galois LFSR generator written in MyHDL with max-cycle tap positions for selected widths. An table of taps for selected widths is used to…

License : LGPL
Language : Other
Gregory-Newton Extrapolation Algorithm (GN Extrapolator)

Gregory-Newton Extrapolation Algorithm (GN Extrapolator)

This project is developed at Reconfigurable Computer Laboratory - FRM - UTN, and allows simulate and synthesize the Gregory-Newton extrapolation…

License : LGPL
Language : VHDL
Synthesizeable Pipelined Hardware Dividers

Synthesizeable Pipelined Hardware Dividers

This is a collection of synthesizeable hardware dividers. Different types of dividers are available. All dividers are fully pipelined and provide a…

HCSA Adder and Generic ALU based on HCSA

HCSA Adder and Generic ALU based on HCSA

Hierarchical Carry Save Algorithm (HCSA) is a modification of well known adder algorithm. Comes as VHDL IP core, shows good timing and small area…

Huffman Decoder for Streaming Application

Huffman Decoder for Streaming Application

Huffman code is used in the most streaming applications. I have written a Huffman decoder for jpeg pictures. For audio or other data streams the…

License : Others
Language : VHDL
Heap Sorter Algorithm for FPGA

Heap Sorter Algorithm for FPGA

This project implements a sorter able to sort a continuous stream of data, consisting of records labeled with "sort keys". Sorter sorts…

License : BSD
Language : VHDL
HIERARCHICAL Integer Multiplier Unit

HIERARCHICAL Integer Multiplier Unit

Before You read This is a brief overview of the article about the series of multiplication algorithms. For comparison and estimation of proposed…