VHDL implementation of the XTEA block cipher (iterative architecture).
Canny edge detector with a 9x9 mask (gradient + gaussian filtering with sigma = sqrt(2)). Able to produce a throughput of 1 pixel per clock cycle.…
This is a Verilog implementation of the XTEA block cipher. It works on two 32-bit blocks of data at a time with a 128-bit key. A proper OpenCores…
Adaptive LMS Equalizer In communication systems channel poses an important role. channels can convolve many different kind of distortions to our…
WDSP project includes three System on Chip (SoC) cores, which implement the Digital Signal Processing (DSP) functions: Finite Impulse Response…
The circuits found here implement digital leapfrog filters as described in <http://en.wikibooks.org/wiki/Signal_ProcessingDigital_Filters>.…
The difference equation for the biquad filter is: y[n] = b10*x[n] + b11*x[n-1] + b12*x[n-2] + a11*y[n-1] + a12*y[n-2] This equation is implemented…
Cores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into…
FIR filter - architecture written with pure verilog - parameterizable in verilog code - cascaded - processing is paralleled - data and coefficients…
This is a structural model for cascaded integrator comb (CIC) decimation filters. The filter consists of integrator, downsampler and comb stages.…
CIC filter It is the CIC filter with Hogenauer pruning. This project is based on https://opencores.org/projects/cic_core project. Differences are…
Cascaded integrator-comb (CIC) digital filters are computationally efficient implementations of narrowband lowpass filters and are often embedded…
This is an elementary generic structural VHDL code for FIR digital filters in transposed-form and direct-form implementations. This project covers…
The DDS IP core (dds_synthesizer) is a implementation of a direct digital frequency synthesizer (DDS) (also called number controlled oscillator,…
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The goal of this project is to create an IP core for an FFT that runs, in a pipelined fashion, at two samples per clock. A C++ program will…
VHDL core generator FIRGEN Project generates optimized VHDL codes for FIR Filters and Multiplier arrays using "Nonrecursive Signed Common…
Integer streaming FFT fixed size and resizable. Language - SystemVerilog. Generator of rotation coefficients in MatLab. Includes Quartus project…
A fully configurable VHDL Viterbi decoder compliant with the AXI4-Stream interface. Most standards using convolutional codes like Wifi or GSM are…
The RTL computes Fast Hadamhard Transform of 8-bit input data. The code has been developed using standard FHT algorithm using matrix addition. The…
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