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Category: All IP Cores (1032)

Attiny Atmega Xmega Configurable Atmel Core Processor

This is a configurable Atmel processor and support eight configurations: 1) REDUCED 2) MINIMAL 3) CLASSIC_8K 4) CLASSIC_128K 5) ENHANCED_8K 6)…

License : LGPL
Language : Verilog

Two 8-bit Timer/Counters AVR Core

Microcontroller core compatible with one used in AT mega 103 and written in VHDL. It has the same instruction timing and the same instruction set…

AVR HP - Hyper Pipelined AVR Core

The project is based on OpenCores' AVR project by Ruslan Lepetenok. The core is now hyper pipelined. It is a technique to multiply the…

License : LGPL
Language : VHDL

AVRtinyX61core - Atmel AVR ATtiny261/461/861 Compatible Core

This is a Atmel AVR ATtiny261/461/861 compatible core. It should be (more or less) fully code compliant, but it is not clock-cycle compliant. The…

License : LGPL
Language : VHDL

AX8 MCU - Microcontroller Compatible with 90S1200 and 90S2313

Microcontroller core compatible with 90S1200 and 90S2313. Same instruction timing as in the original MCUs. Both MCUs use the configurable AX8 core.…

Brainfuck CPU - Hardware Implementation

Brainfuck CPU is a hardware implementation of Brainfuck programing language. It uses simple 2-stage pipelining and Harvard's architecture. This…

License : LGPL
Language : Verilog

CF State Space Processor

Cores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into…

ClaiRISC - Soft MCU Core Runs 12bit Opcode PIC Family

This ClaiRISC is a soft MCU core which runs PIC 12bits instruction.Compared with PIC16F57 ,This core has the same number of register file while…

Language : Verilog

Classic 5-Stage Pipeline MIPS 32-bit Processor

A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a 1024 depth branch prediction buffer, a 2KB direct-mapped…

License : BSD
Language : Verilog

Codezero Microkernel OpenRISC Port

Introduction Codezero, L4 microkernel architecture Design principles Benefits The microkernel is the only component that runs in privileged CPU…

License : GPL
Language : C/C++

Confluence OpenRisc 1000 32-bit CPU

This is a new implementation of the OpenRisc 1000 architecture in the Confluence language. Features - OpenRisc 1000 32-bit CPU - ORBIS32-I…

Language : Other

GPU Core Design in VHDL

The graphics processed by the GPU are defined as a set of vertices that contain spatial information, i.e. vectors with coordinates [x y z] in…

License : LGPL
Language : VHDL

Cowgirl - MIPS R3000 Resemblance in VHDL

This is an implementation of an instruction set that I created. It's not a particularly useful thing to do, but it's something I've…

Language : VHDL

R6502 Processor Soft Core with Accurate Timing (Upgraded)

The 65C02 by Rockwell is the upgraded version of the legendary Rockwell's R6502. cpu65c02_tc offers you an accurate timing for all new and…

License : GPL
Language : VHDL

R6502 Processor Soft Core with Accurate Timing

This is a VHDL/Verilog IP core with True Cycle Timing for Rockwell's 6502 8-Bit CPU. With full functional input signals like ready, interrupt,…

License : GPL
Language : VHDL

Diogenes: Student RISC System

This Project was developed within a Computer Architecture Course. It demonstrates a simple RISC architecture. Please note that it was developed on…

Language : VHDL

DFP Flexible Data Flow Microprocessor in VHDL

The data flow processor (DFP) is a flexible microprocessor written in VHDL which you can program down to the gate level to optimize your entire…

Language : VHDL

openMSP430 - Synthesizable 16-bit Microcontroller Core

Introduction The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' MSP430…

License : BSD
Language : Verilog

Distributed Limited Cores

simple alu

License : LGPL
Language : VHDL

ECPU Arithmetic Logic Unit (ALU) in Verilog

Comments # ECPU 0.1.alpha # ============== # # Background # ======== # Resurrected university project originally written in VHDL. # Converted to…

License : GPL
Language : Verilog