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Category: All IP Cores (1032)

UCore MIPS32R2 Compatible RISC Microprocessor

UCore MIPS32R2 Compatible RISC Microprocessor

UCore is a RISC microprocessor compatible of the MIPS32R2 Instruction Set. It can run all the MIPS32R2 instructions except the branch likely…

Language : Verilog
VTACH - Bell Labs CARDIAC Reimagined in Verilog

VTACH - Bell Labs CARDIAC Reimagined in Verilog

Verilog implementation of the old CARDIAC teaching computer from Bell (the one made out of cardboard). This version runs on a Spartan 3 board from…

License : LGPL
Language : Verilog
VHDL Core of IC6821 Emulator

VHDL Core of IC6821 Emulator

emulating the IC6821 One day my partern says lets make this old board smaller. But a lot of IC6821. So emulate them into an FPGA. So i developed…

License : GPL
Language : VHDL
YACC - MIPS I (TM) subset CPU in Verilog-2001 HDL

YACC - MIPS I (TM) subset CPU in Verilog-2001 HDL

YACC (Yet Another CPU CPU) is MIPS I (TM) subset cpu written in Verilog-2001 HDL. YACC has 5 pipeline and shows 110 DMIPS in stratix2 with…

Language : Verilog
Wishbone BFM for Modelsim 6.2g and Xilinx ISE 9.2 sp4

Wishbone BFM for Modelsim 6.2g and Xilinx ISE 9.2 sp4

VHDL reads a file of instructions to perform Wishbone access, as if it's a wishbone master. Used in testing a Wishbone peripheral with out…

License : LGPL
Language : VHDL
Y80e - Z80/Z180 Compatible Processor Softcore

Y80e - Z80/Z180 Compatible Processor Softcore

Z80/Z180 compatible processor softcore. Based on Y80 project described in the book 'Microprocessor Design Using Verilog HDL' of Monte…

License : BSD
Language : Verilog
Asynchronous Spatial Division Multiplexing Router for NoCs

Asynchronous Spatial Division Multiplexing Router for NoCs

Asynchronous Spatial Division Multiplexing Router for On-Chip Networks Version: 0.2 On-chip networks or networks-on-chip (NoCs) are the on-chip…

License : LGPL
Language : Verilog
ECO32 32-bit RISC Microprocessor SoC

ECO32 32-bit RISC Microprocessor SoC

The ECO32 system is a microprocessor system-on-chip, consisting of a 32-bit CPU and several controllers for peripheral devices (keyboard, character…

License : BSD
Language : Verilog
Yellow Star - 32 bit R2000/R3000 Processor Implementation

Yellow Star - 32 bit R2000/R3000 Processor Implementation

It is capable of executing 32bit instructions based on the MIPS R3000 microprocessor instruction set and has been tested running large blocks of…

Infocom Z-Machine V3 | Z3 - The Zork CPU

Infocom Z-Machine V3 | Z3 - The Zork CPU

A Verilog implementation of the Infocom Z-Machine V3. The spec the Z3 follows is http://inform-fiction.org/zmachine/standards/z1point0index.html.…

License : BSD
Language : Verilog
z80control System for PLC and PC Connection via Serial Interface

z80control System for PLC and PC Connection via Serial Interface

Microprocessor targeting embedded industrial control systems. Uses a z80 core available at opencores as T80. It is in early development stages. It…

License : GPL
Language : VHDL
Zet x86 (IA-32) Open Implementation

Zet x86 (IA-32) Open Implementation

The Zet SoC PC platform and processor is an open implementation of the so widely used x86 architecture. This project is being developed using four…

License : GPL
Language : Verilog
GECKO3 SoC General Purpose Co-design Environment

GECKO3 SoC General Purpose Co-design Environment

The GECKO system is a general purpose hardware/software co-design environment for real-time information processing and/or system-on-chip (SoC)…

License : Others
Language : VHDL
AHB to Wishbone Protocol Bridge

AHB to Wishbone Protocol Bridge

AHB Protocol to Wishbone Protocol Bridge. Features - AHB 2.0 compliant - Wishbone B.3 compliant - AHB Burst NOT SUPPORTED - Fully synthesisable -…

Language : Verilog
ZPU - Worlds Smallest 32 bit CPU with GCC Toolchain

ZPU - Worlds Smallest 32 bit CPU with GCC Toolchain

The worlds smallest 32 bit CPU with GCC toolchain Read about some of the professional uses of the ZPU: http://www.zylin.comzpuexpertise.html The…

Language : Other
32/64 bits AHB Master DMA Core

32/64 bits AHB Master DMA Core

Single channel 32 or 64 bit AHB master DMA core. Supports simultaneous read and write, command lists, peripheral control, timeouts and endianess…

License : LGPL
Language : Verilog
AMBAtm Specification Compliant AHB System Generator

AMBAtm Specification Compliant AHB System Generator

The intention is to provide an easy way to configure, create and simulate a "complete" AHB system. The main block is the "AHB…

License : LGPL
Language : VHDL
Minimal OpenRISC System on Chip Implementation

Minimal OpenRISC System on Chip Implementation

The Minimal OpenRISC System on Chip is a system on chip (SoC) implementation with standard IP cores available at OpenCores. This implementation…

License : LGPL
Language : Verilog
aoOCS - Wishbone Amiga OCS SoC Implementation

aoOCS - Wishbone Amiga OCS SoC Implementation

The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is…

License : BSD
Language : Verilog
Open Source ARM VHDL Model

Open Source ARM VHDL Model

A open source ARM vhdl model. The annotated vhdl source can be browsed here: http://cfw.sourceforge.net/build_html/vhdl/index.htm Features Note:…

Language : VHDL