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32/64 bits AXI master DMA Core

32/64 bits AXI master DMA Core

Single channel 32 or 64 bit AXI master DMA core. Supports simultaneous read and write, outstanding AXI commands, command lists, peripheral control,…

License : LGPL
Language : Verilog
AXI4 Transactor and Bus Functional Model Implementation in VHDL

AXI4 Transactor and Bus Functional Model Implementation in VHDL

This project implements the AXI4 transaction-level model (TLM) and bus functional model (BFM) in VHDL. Currently, only the AXI4-Stream Master…

License : LGPL
Language : VHDL
CMOD S6 SoC for ZipCPU Soft Core Implementation

CMOD S6 SoC for ZipCPU Soft Core Implementation

This CMOD-S6 SoC grew out of the desire to demonstrate that a useful ZipCPU soft core implementation could be made in a very small space. In…

License : GPL
Wishbone Version : B.4
Language : Verilog
Software Defined Radio CCSDS RX/TX SoC

Software Defined Radio CCSDS RX/TX SoC

Software Defined Radio RX/TX. Consultative Committee for Space Data System (CCSDS) specifications compliant. This is part of a larger project…

License : Others
Language : VHDL
System-On-Chip Based on Bare Rocket-chip (RISC-V ISA)

System-On-Chip Based on Bare Rocket-chip (RISC-V ISA)

Common top-level structure. * CPU: Single core "Rocket-chip": 64-bits CPU (RISC-V ISA) with L1/L2 caches, MMU, TLBs, 128-bits data bus…

License : BSD
Language : VHDL
CPU Lecture SoC in VHDL

CPU Lecture SoC in VHDL

Overview This is a lecture about designing a SoC in VHDL. Everything runs under Linux - no more Windows! Check it out and then start at the file…

License : GPL
Language : VHDL
Embedded 32-bit Mini RISC uProcessor with SDRAM Controller

Embedded 32-bit Mini RISC uProcessor with SDRAM Controller

Embedded 32-bit mini RISC uProcessor project with SDRAM controller will develope a basic block IP (Intellectual Properties) for designing a…

Embedded FPGA Architecture Core

Embedded FPGA Architecture Core

Architecture Description Field-Programmable Gate Arrays (FPGAs) are flexible and reusable high-density circuits that can be (re)configured by the…

16-bit Experimental Unstable CPU with a Simple Bus System

16-bit Experimental Unstable CPU with a Simple Bus System

A simple 16-bit microprocessor together with a simple bus system. It utilises the Xilinx dual port ram features to be able to fetch instructions…

License : LGPL
Language : VHDL
Z80 System on Chip for Altera DE1 and Diligent Spartan 3E

Z80 System on Chip for Altera DE1 and Diligent Spartan 3E

Z80 System on Chip System on chip, based on T80 core. This project is a SOC designed for Altera DE1 development board and the Diligent Spartan 3E,…

Language : VHDL
Generic APB Register File Generator

Generic APB Register File Generator

Generic APB register file generator. Creates Verilog source, C header file and HTML documentation, from an Excel worksheet. The source files are…

License : LGPL
Language : Verilog
H2 System-On-Chip VHDL based on J1 CPU

H2 System-On-Chip VHDL based on J1 CPU

The H2 is a System On a Chipc (SoC) built around a stack processor that can directly execute Forth called the H2. The system is written in VHDL and…

License : Others
Language : VHDL
Wishbone to I2C Controller Wrapper

Wishbone to I2C Controller Wrapper

Short: virtually convert an I2C slave into a WISHBONE slave This is a wrapper for the I2C controller core by Richard Herveille…

License : LGPL
Language : VHDL
ProNoC GUI MCSoC Generator

ProNoC GUI MCSoC Generator

Project Summary Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC…

License : LGPL
Language : Verilog
Internal Communication Bus for FPGA

Internal Communication Bus for FPGA

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : BSD
Language : VHDL
Keras to FPGA SoC

Keras to FPGA SoC

Description Implements Dense ANN that can directly use the weights from Keras. Still need to add SoftMax, MaxPooling, Conv2D & LSTM The url of…

License : LGPL
Language : Verilog
MIPS I 512 MBit DDR Ram layer 2 SoC

MIPS I 512 MBit DDR Ram layer 2 SoC

The following components are implemented and tested on silicon: MIPS I(tm) CPU @ 50MHz Intel StratFlash PS/2 Keyboard 100x37 8-Color Text-VGA…

License : GPL
Language : VHDL
M16C5x Soft-core Processor

M16C5x Soft-core Processor

This project demonstrates the use of the P16C5x soft-processor core, found elsewhere on opencores.org, in a system-on-chip. The project targets a…

License : LGPL
Language : Verilog
Next186 Core SoC PC

Next186 Core SoC PC

PC AT SoC based on Next186 core. CPU runs at up to 80 MHz (80 MIPS), up to 64MB of RAM, HMA available. Able to run DOS6.22, FreeDos, Windows3.0,…

License : LGPL
Language : Verilog
MP3 Decoder in VHDL

MP3 Decoder in VHDL

This project is to implement an MP3 decoder in VHDL in terms of MPEG-1 layer3 standard. It is composed of all the components of MP3 decoding…