Microcontroller core compatible with 16C55 and 16F84. Single cycle VHDL implementations of 16C55 and 16F84. Four times faster than the original…
Project Qrisc32 is academic research and implementation of 4 stages risc cpu. Testbench runs 3 different sorting algorithms on qrisc32 and shows…
Raptor64 is a 64-bit multi-context RISC cpu that supports hyper-threading. There are 16 register sets that the processor automatically switches…
The project is microprocessor (uP) architectural exploration with a goal of a high performance FPGA soft core processor(s) over a range of word…
This CPU project does not implement fully AVR compatible core. Instead it realizes very minimal functionality. Task was to make kind of CPU that…
The risc16f84 project is intended to provide a small, easy to use microcontroller in Verilog. The original code was VHDL, but I have done a…
A small RISC CPU (written in VHDL) that is compatible with the 12 bit opcode PIC family. Single cycle operation normally, two cycles when the…
This project is an implementation of a processor compatible with the instruction set of the RISCO architecture. A description of the original RISCO…
RV01 is a two-way in-order superscalar processor core implementing RISC-V RV32I instruction set with “M” extension according to RISC-V…
This is a 4 stage 16-Bit RISC processor system on chip designed for a Xilinx Virtex FPGA. RAM and ROM both are blockRAM based. Additionally, it is…
RISE (Rarest Instruction Set Ever) is a pipelined 16-bit RISC processor with a simple instruction set. One outstanding feature of the instruction…
The RTF65002 is a 32 bit processor with an instruction set influenced by the 6502 instruction set. It is a 16 register 32 bit word oriented design.…
rtf8088 is a core capable of executing the 8088 instruction set. The core uses a hard-wired state machine approach.
The S80186 IP core is a compact, 80186 binary compatible core, implementing the full 80186 ISA suitable for integration into FPGA/ASIC designs. The…
The T48 µController core is an implementation of the MCS-48 microcontroller family architecture. While being a controller core for SoC, it…
Summary SSBCC.9x8 is a free Small Stack-Based Computer Compiler with a 9-bit opcode, 8-bit data core. It creates vendor-independent, high-speed,…
The SAYEH processor (Simple Architecture,Yet Enough Hardware) has been designed for educational and benchmarking purpose. Relying on the material…
Overview Theia GPU Overview Theia is a fully programmable Graphic Processing Unit written in structural Verilog Theia features a multi-core…
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sub86 is a frugal 32bits cpu that executes a small subset of the legacy x86-32 instructions. The core has been designed with a C compiler back end…
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