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A 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is presented. The design can handle 5 different channels at an input…
This is a behavioral module for parallel scrambler/descrambler. There are RTL scrambler modules available, the purpose of this project is to built…
The CORDIC algorithm is an iterative algorithm to evaluate many mathematical functions, such as trigonometrically functions, hyperbolic functions…
Free and open source double precision Floating Point Unit (FPU). The openFPU64 currently features: - double precision - Addition/Subtraction -…
Quadratic_func is a fully pipelined quadratic polynomial that computes the relation y = ax^2 + bx + c. On each rising-edge of the clock (when en is…
VHDL implementation of a fast space- and resource-efficient logarithm approximation unit for FPGAs. The unit is an implementation of the ICSILog…
VHDL project for a Square Root Unit (SRU) for 32-bit fixed point data. The unit implements the Goldschmidt recursion algorithm. It is pipelined…
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This project implements the Galois Linear-feedback Shift Register (LFSR) in VHDL, and can be used for applications such as PRBS generation &…
This IP core allows lossless data compression based on the Lempel-Ziv-Ross-Williams-1 algorithm. Its focus is on high throughput (of uncompressed…
This project is developed at Reconfigurable Computer Laboratory - FRM - UTN, and allows simulate and synthesize the Gregory-Newton extrapolation…
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The lfsr core is a random number generator based on linear feedback shift register(LFSR).The sequence generated has the maximum length possible.The…
the aim of this design to build combinatorial digital circuit to find in fast parallel the maximum or the minimum of set of given set data where…
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QFP32 Arithmetic Core implements a full customizable arithmetic core using the QFP32 format. Available arithmetic operations are easily configured…
Ray Tracing : A rendering technique that challenges anyone who is interested in Computer Science, Computer Graphics and Digital Systems in General.…
VHDL Implementation of a basic Pipeline MIPS processor. It has a translator of MIPS assembler code and implement the division algorithm restoring.
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The module expects ASCII character code (in 8-bit binary) and displays the coresponding character on single digit 14-segment monocolor LED display.…
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