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Here is proposed a method to implement short structured programs inside an FPGA. The novelty of the proposed method resides in that the commands…
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Generic AHB matrix. It is a multi-master, multi-slave non-blocking AHB matrix with round-robin arbitration. Builds Verilog AHB matrices according…
Generic AXI interconnect fabric. It is a multi-master, multi-slave non-blocking AXI fabric with round-robin arbitration. Builds Verilog AXI…
Generic AXI to AHB bridge. Built according to input parameters: AXI command depth, data bits, etc. Supports error on illegal AHB bursts and AHB…
Generic AXI to APB bridge. Builds design according to required number of slaves, address decoding, AXI command depth, etc. Supports decode error,…
This project is to implement a SoC of using OpenRISC 1200 and many open source IP cores from opencores.org on Nios II Embedded Evaluation Kit…
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks Version: 0.2 On-chip networks or networks-on-chip (NoCs) are the on-chip…
Single channel 32 or 64 bit AHB master DMA core. Supports simultaneous read and write, command lists, peripheral control, timeouts and endianess…
The intention is to provide an easy way to configure, create and simulate a "complete" AHB system. The main block is the "AHB…
The Minimal OpenRISC System on Chip is a system on chip (SoC) implementation with standard IP cores available at OpenCores. This implementation…
Single channel 32 or 64 bit AXI master DMA core. Supports simultaneous read and write, outstanding AXI commands, command lists, peripheral control,…
This project implements the AXI4 transaction-level model (TLM) and bus functional model (BFM) in VHDL. Currently, only the AXI4-Stream Master…
A simple 16-bit microprocessor together with a simple bus system. It utilises the Xilinx dual port ram features to be able to fetch instructions…
Generic APB register file generator. Creates Verilog source, C header file and HTML documentation, from an Excel worksheet. The source files are…
Short: virtually convert an I2C slave into a WISHBONE slave This is a wrapper for the I2C controller core by Richard Herveille…
Project Summary Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC…
Description Implements Dense ANN that can directly use the weights from Keras. Still need to add SoftMax, MaxPooling, Conv2D & LSTM The url of…
This project demonstrates the use of the P16C5x soft-processor core, found elsewhere on opencores.org, in a system-on-chip. The project targets a…
PC AT SoC based on Next186 core. CPU runs at up to 80 MHz (80 MIPS), up to 64MB of RAM, HMA available. Able to run DOS6.22, FreeDos, Windows3.0,…
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