Compact and optimized PS/2 controller for Keyboard and Mice. PS2 Core is build modular. There are one principal module that contains all…
This is a very simple project for reading a quadrature device, such as an optical encoder. The counter is initialized to zero, and then counts up…
This is a small UART to byte uPC interface (compliant with RS232 and RS3232 CI's). Ideal to use with soft/hard processors in a FPGA project.…
This SATURN protocol stack constitutes the low level communication layers necessary to implement a SATURN compatible network. The project is split…
SATA PHY layer which can be implemented as either a host or device for Xilinx 6 series devices. A host controller core with AXI interface is…
Two wire RS232 communication module capable of 5, 6, 7, 8 bit word communication, Parity bit, Parity bit Polarity, 1 and 2 stop bits. Integrated…
This is a simple uart core which includes a baud generator. The core uses a fixed format: 1 start,8 data, 1 stop bit. + baudX8/X16 mode selects in…
Overview RXAUI interface uses two 6.25Gbps SERDES lanes to carry 10GE, instead of using four 3.125Gbps SERDES lanes. This enables a high port count…
Sata stack written in Verilog , , Staus: , , , ,Nysa SATA Github, , , Code Organization: , , sata_stack.v (Top File that applications interface…
This project includes three main VHDL packages: sd_card_pack.vhd = A synthesizable SD/eMMC/MMC emulator with all card registers, including EXT_CSD…
USBHostSlave is a USB 1.1 Host and Function IP core. It supports full speed (12Mbps) and low speed (1.5Mbps) operation, and supports the four types…
This is a scan based serial communication block designed to safely and easily move data onto and off of a chip with a minimal number of pins.…
SD (Secure Digital) and MMC memory card controller with Wishbone slave interface. Handles all aspects of card initialization, 512 byte block read,…
The core is a combined SD/SDHC controller, for Secure Digital-card. Two designs is available, one full-feature core utilizing DMA and one smaller…
The SD/MMC Bootloader is a CPLD design that manages configuration and bootstrapping of FPGAs. It is able to retrieve the required data from…
Design in VHDL: This UART is able to Transmit/Receive bytes in the configuration: 1 start bit - no parity - 1 stop bit. It can be commanded by a…
Please write a description of the project here. It is used as a MetaTag (search engines looks at this).
The SATA core implements the Command, Transport and Link Layers of the SATA protocol and provides a Physical Layer Wrapper for the GTX…
SDRAM Controller (AXI4) Github: https://github.com/ultraembedded/core_sdram_axi4 This IP core is that of a small, simple SDRAM controller used to…
Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing…
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