KLC32 is a 32 bit non-pipelined processor. This project is in the first stage of it's evolution and has a long ways to go yet, hence…
Overview Summary This document describes my implementation of a 6502 microprocessor into a Lattice LCMXO2280C FPGA. The hardware is based on an…
LEM1_9min documentation Four new variants of LEM1_9 are now implemented: LEM1_9 Call/Return/Conditional branches implemented along with a return…
Yet another free 8051 FPGA core. This is a 6-clocker-equivalent implementation of the MCS51 architecture, aiming at area performance. A full…
LXP32 is a lightweight, open source and FPGA-friendly 32-bit CPU IP core. It uses a simple, original instruction set designed for straightforward…
This is a simple, small microprogrammed Intel 8080 CPU binary compatible core. There are already at least two other 8080-compatible cores in…
This is a design that mixes processor and memory on a single chip. There are a bunch of operations surrounded by buffers. A central unit tells the…
Leros-32 is a 32-bit ALU port of the Leros project. It contains an icache and dcache implementation and interface for Xilinx based memory…
This project provides a microprogrammed synthesizable IP core compatible with the WDC and Rockwell 65C02 microprocessors. This project demonstrates…
M1 Core briefly... The M1 Core is a 32-bit RISC CPU compatible with a popular GCC target. It's been designed for simplicity and it's been…
M32632 is an implementation of the Series 32000 architecture of National Semiconductor. This 32-bit architecture was popular in the 1980's and…
This is an implementation of a Digital (DEC) PDP8/L processor with 4k memory, a single DF32 disk and serial interface. The project target is the…
Introduction The MB-Lite microprocessor is a ligth-weight implementation of the Microblaze Instruction Set Architecture. It is instruction and…
This module is a 6803 CPU based on System68 and System01 by John E. Kent. I have translated the CPU core from VHDL to SystemVerilog and added some…
McAdam's RISC Computer Architecture (marca) is a simple 16-bit microprocessor, implementing a load/store instruction set architecture and…
Introduction MCIPopen is a light version of MCIP microcontroller IP core. It has a simple architecture compatible with Microchip PIC18 MCUs.
MCPU - Minimal CPU for a 32 Macrocell CPLD MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD - one of the smallest available programmable…
Description of project..
32 Bit RISC Processor, 5 Stage Pipeline. Developed for embedded control of devices. Optimized for the Xilinx SpartanII and Virtex line of…
This project is developed at Reconfigurable Computer Laboratory - FRM - UTN, and allows simulate and synthetize the Simplez processor. It is a…
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