Latest IC Design Industry White Papers

Learn how to quickly and accurately analyze and fix (or waive) a wide range of complex error conditions with automated…

Learn how to quickly and accurately analyze and fix (or waive) a wide range of complex error conditions with automated post-processing DRC debugging flows.

This whitepaper takes a closer look at how the ADC brings together space and ground-based telescopes in search of answers…

This whitepaper takes a closer look at how the ADC brings together space and ground-based telescopes in search of answers to the biggest questions that we have about our universe.

This white paper explores the concepts around a typical safety island implementation along with examples of how it can be used.

This white paper explores the concepts around a typical safety island implementation along with examples of how it can be used.

This paper outlines the multi-dimensional nature of this complexity and the costs and opportunities it generates. It also…

This paper outlines the multi-dimensional nature of this complexity and the costs and opportunities it generates. It also demonstrates that the key to designers meeting this challenge is the ability to attain system-level visibility: both during the semiconductor development cycle, and subsequently after embedded systems are deployed in the field.

This paper explains the drivers and benefits of implementing PLM practices into the semiconductor industry. This…

This paper explains the drivers and benefits of implementing PLM practices into the semiconductor industry. This resource also provides a detailed description of the elements that make up the Tessent Silicon Lifecycle Solutions platform.

This white paper displays how the Tanner flow simplifies the design and verification process of Analog/Mixed-Signal…

This white paper displays how the Tanner flow simplifies the design and verification process of Analog/Mixed-Signal design. It also describes how the user can verify design functionality, connectivity, and performance at all levels of the design hierarchy and for all integrated circuit (IC) applications.

This white paper walks through the design and review of a wiring harness for a small tractor using VeSys. Solutions like…

This white paper walks through the design and review of a wiring harness for a small tractor using VeSys. Solutions like the one discussed in this resource allow vehicle manufacturers to meet the demands of product complexity and quality while going to market faster than ever.

In this white paper, the reader will learn how the Calibre tools provide enhanced verification and fill optimization…

In this white paper, the reader will learn how the Calibre tools provide enhanced verification and fill optimization that can drastically reduce the number of simulations required. It also discusses how the tools achieve the aforementioned while still ensuring designs will perform reliably in conformance with their design specifications over the lifetime of the products in which they are used. 

This white paper outlines how to simplify the analog management process by rolling all the tasks into a single tool that…

This white paper outlines how to simplify the analog management process by rolling all the tasks into a single tool that also enables the visualization of results in spreadsheets.

Explore this step-by-step approach to building a CTSD modulator loop starting with the widely known closed-loop inverting…

Explore this step-by-step approach to building a CTSD modulator loop starting with the widely known closed-loop inverting amplifier configuration and combining it with an ADC and a DAC.

This whitepaper dives into the qualities and features of ROHM's latest musical IC ― the MUSIC™ BD34301EKV, a…

This whitepaper dives into the qualities and features of ROHM's latest musical IC ― the MUSIC™ BD34301EKV, a high-resolution audio digital-to-analog converter (DAC). This component, along with an array of others (including a high-fidelity power supply and sound processor), offers the basic building blocks of a Hi-Fi audio device.

Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern…

Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern generation (ATPG) and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected don’t consider the likelihood of one fault occurring compared to another.

This white paper describes the basic components of the Tessent Streaming Scan Network (SSN), a technology designed to…

This white paper describes the basic components of the Tessent Streaming Scan Network (SSN), a technology designed to decouple core level and chip level DFT requirements. With SSN, DFT engineers can for the first time implement DFT using a true, effective bottom-up flow, not having to make trade-offs between implementation effort and manufacturing test cost.

This white paper demonstrates how using a production 7nm design, AMD achieved a 2.5X speed up in physical verification cycle time.

This white paper demonstrates how using a production 7nm design, AMD achieved a 2.5X speed up in physical verification cycle time.

This white paper takes a look at how to replace inefficient, less precise verification processes with smarter, more…

This white paper takes a look at how to replace inefficient, less precise verification processes with smarter, more accurate, faster, and more efficient functionality that can improve both the bottom line and product quality.

This white paper evaluates the necessity and value of EDA in the cloud while providing a cost-benefit breakdown.…

This white paper evaluates the necessity and value of EDA in the cloud while providing a cost-benefit breakdown. Additionally, explore how companies can establish guidelines to ensure that usage is as efficient and cost-effective as possible.

This white paper discusses faults and detectability by a safety mechanism, safety mechanism types and attributes, and how…

This white paper discusses faults and detectability by a safety mechanism, safety mechanism types and attributes, and how safety mechanism effectiveness is evaluated.

This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP solution can be…

This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP solution can be used with multiple types of hosts by supporting legacy PCIe 4.0, USB4, USB 3.x, and USB 2.0 connections.

This paper provides an overview of the key characteristics of ON Semiconductor Gen 1 1200 V SiC MOSFETs and how they can…

This paper provides an overview of the key characteristics of ON Semiconductor Gen 1 1200 V SiC MOSFETs and how they can be influenced by the driving conditions. This resource also provides a guideline on the usage of the NCP51705 an isolated gate driver for SiC MOSFETs.