Many evolutionary changes have allowed DRAM cell size to shrink to 0.0020 um2. At sub-15nm nodes, DRAM designs require optimization to avoid some of the common failure modes like Variable Retention Time, Sensing Fails, Row Hammer, Row Press, and Sensing Fails.
In partnership with Neumonda
The standard DRAM tests of memory manufacturers often don’t meet industrial requirements. The new Rhinoe tester from NEUMONDA conducts vendor-independent tests that simulate the environment the DRAM will be used in to predict potential failures. All this at a fraction of the costs of traditional testers. This is unique.
In partnership with Neumonda
DDRx memory interfaces are key enablers for the technology that shapes modern life. Servers, computers, smartphones, gaming consoles, and GPS systems are just some of the products that demand high-speed, high-bandwidth, double-data-rate memory. Each generation of DDRx DRAM brings new advantages that allow for faster, higher-capacity, and lower-power-consumption products.
May 04, 2021 by Siemens Digital Industries Software
In today’s hyper-connected world, transmitting and receiving information between different locations has become commonplace. The internet has provided access to unlimited streams of information accessible on mobile phones, personal computers, gaming consoles, wearables, and more.
March 21, 2021 by TAIYO YUDEN
January 29, 2021 by Rohde & Schwarz
December 23, 2019 by Newark
October 16, 2019 by Arm
