Latest Digital ICs Industry White Papers

Critical Area Based Test Pattern Optimization

Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern generation (ATPG) and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected don’t consider the likelihood of one fault occurring compared to another.

Streaming Scan Network: A No-Compromise Approach to DFT

This white paper describes the basic components of the Tessent Streaming Scan Network (SSN), a technology designed to decouple core level and chip level DFT requirements. With SSN, DFT engineers can for the first time implement DFT using a true, effective bottom-up flow, not having to make trade-offs between implementation effort and manufacturing test cost.

Siemens, AMD, and Microsoft Collaborate on EDA In the Cloud

This white paper demonstrates how using a production 7nm design, AMD achieved a 2.5X speed up in physical verification cycle time.

EDA In the Cloud—Now More Than Ever

This white paper evaluates the necessity and value of EDA in the cloud while providing a cost-benefit breakdown. Additionally, explore how companies can establish guidelines to ensure that usage is as efficient and cost-effective as possible.

Rethinking Applications Processing for Ultra-Low Power - i.MX 7ULP

This white paper discusses how NXP was able to reduce power without severely compromising features and performance dramatically. It also provides a closer look at how the i.MX 7ULP applications processor brings the benefits of a rich OS to battery-powered devices.

Flexible USB4-based Interface IP Solution for AI at the Edge

This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP solution can be used with multiple types of hosts by supporting legacy PCIe 4.0, USB4, USB 3.x, and USB 2.0 connections.

Mentor, AMD, and Microsoft Collaborate on EDA in the Cloud

Moving some or all of your electronic design automation (EDA) computing to the cloud enables your company to reduce time-to-market and innovate faster, simply by taking advantage of flexible resources and economies of scale.

Spartan-7 SP701 FPGA Evaluation Kit Demonstration Project

Developing cost-effective industrial image processing systems requires high-performance cameras and flexible image-processing systems capable of adaption.

Source Control, Git, and Industrial Automation

Source control systems have become ubiquitous in the IT world but have not become a major component of operational technology (in particular, PLC programming). There is an increasing, popular movement in the industrial controls world to bring modern source control systems to PLC programming.

Jitter Budgeting for Clock Distribution Networks in High-Speed PHYs and SerDes

High speed PHYs, such as industry’s recent DDR5/LPDDR5 operating at 6400 Mbps and high-speed SerDes, heavily rely on on-die clock distribution networks for clock and data transmission.

Addressing the Evolving Technology Needs of Cloud Data Centers with IP

The advent of cloud computing nearly 20 years ago has led to a steady migration of computational resources from corporate data centers to the cloud.

Accelerate Time to Market with Calibre nmLVS Recon Technology: A New Paradigm for Circuit Verification

One thing is clear — tapeouts are getting harder and taking longer. According to statistics from industry conference surveys, at least 50% of scheduled tapeouts slip each year.

Net Common Resistance Extraction is Crucial to Design Reliability

Accurately extracting and calculating the common resistance of interconnects within analog IC designs is fundamental for evaluating circuit reliability, particularly for noise and voltage drop analysis and ESD protection verification.

Optimizing the Integration of DFM and P&R

Design companies and foundries are constantly modifying their design implementation flow to deliver the best possible solution for their operational needs and the best possible designs for the market.

Improving Productivity With More Efficient LVS Debug

Layout versus schematic (LVS) verification is an essential and integral part of integrated circuit (IC) verification in a system-on-chip (SoC) design cycle, but with today’s highly dense and hierarchical layouts, increasing circuit complexity, and intricate foundry rules, running LVS can be a time-consuming and resource-intensive endeavor.

How to Successfully Calibrate an Open-Loop DAC Signal Chain

The monitoring and testing of a DAC signal chain are critical considerations for open-loop applications. Errors in a DAC signal chain, including DAC intrinsic errors that vary depending on the system, can significantly disrupt the customer design-in experience.

Power-Up Phase Determinism Using Multichip Synchronization Features in Integrated Wideband DACs and ADCs

The integration of multiple digital signal processing (DSP) blocks, wideband digital-to-analog converters (DACs), and wideband analog-to-digital converters (ADCs) within a single monolithic chip are enabling the offloading of FPGA resources.

Power-Up Phase Determinism Using Multichip Synchronization Features in Integrated Wideband DACs and ADCs