In this white paper, the reader will learn how the Calibre tools provide enhanced verification and fill optimization that can drastically reduce the number of simulations required. It also discusses how the tools achieve the aforementioned while still ensuring designs will perform reliably in conformance with their design specifications over the lifetime of the products in which they are used.
August 03, 2021 by Siemens Digital Industries Software
Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern generation (ATPG) and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected don’t consider the likelihood of one fault occurring compared to another.
June 17, 2021 by Siemens Digital Industries Software
This white paper describes the basic components of the Tessent Streaming Scan Network (SSN), a technology designed to decouple core level and chip level DFT requirements. With SSN, DFT engineers can for the first time implement DFT using a true, effective bottom-up flow, not having to make trade-offs between implementation effort and manufacturing test cost.
June 17, 2021 by Siemens Digital Industries Software
This white paper evaluates the necessity and value of EDA in the cloud while providing a cost-benefit breakdown. Additionally, explore how companies can establish guidelines to ensure that usage is as efficient and cost-effective as possible.
June 09, 2021 by Siemens Digital Industries Software
This white paper discusses how NXP was able to reduce power without severely compromising features and performance dramatically. It also provides a closer look at how the i.MX 7ULP applications processor brings the benefits of a rich OS to battery-powered devices.
May 18, 2021 by NXP Semiconductors
This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP solution can be used with multiple types of hosts by supporting legacy PCIe 4.0, USB4, USB 3.x, and USB 2.0 connections.
May 12, 2021 by Synopsys
Moving some or all of your electronic design automation (EDA) computing to the cloud enables your company to reduce time-to-market and innovate faster, simply by taking advantage of flexible resources and economies of scale.
May 03, 2021 by Siemens Digital Industries Software
Source control systems have become ubiquitous in the IT world but have not become a major component of operational technology (in particular, PLC programming). There is an increasing, popular movement in the industrial controls world to bring modern source control systems to PLC programming.
April 14, 2021 by Copia Automation
One thing is clear — tapeouts are getting harder and taking longer. According to statistics from industry conference surveys, at least 50% of scheduled tapeouts slip each year.
March 30, 2021 by Siemens Digital Industries Software
Accurately extracting and calculating the common resistance of interconnects within analog IC designs is fundamental for evaluating circuit reliability, particularly for noise and voltage drop analysis and ESD protection verification.
March 30, 2021 by Siemens Digital Industries Software
Layout versus schematic (LVS) verification is an essential and integral part of integrated circuit (IC) verification in a system-on-chip (SoC) design cycle, but with today’s highly dense and hierarchical layouts, increasing circuit complexity, and intricate foundry rules, running LVS can be a time-consuming and resource-intensive endeavor.
March 23, 2021 by Siemens Digital Industries Software
The monitoring and testing of a DAC signal chain are critical considerations for open-loop applications. Errors in a DAC signal chain, including DAC intrinsic errors that vary depending on the system, can significantly disrupt the customer design-in experience.
March 23, 2021 by Analog Devices
