MaaS is driving the need to add and improve features that support the heart of this new technology. This white paper explores how electronics and sensors are powering today's connected vehicles.
March 08, 2022 by Murata
Explore how VirtuaLAB PCIe and Ethernet Virtual Machines (VM) work together, how they compete for host resources and how VMs address the big device management channel requirements for HW and SW co-verification in Veloce emulation.
October 29, 2021 by Siemens Digital Industries Software
This white paper discusses the changes in storage technology and why SSD design teams need a complementary tool kit using ICE, the Veloce Deterministic ICE App, and VirtuaLAB.
October 29, 2021 by Siemens Digital Industries Software
This white paper discusses how SoC verification teams can achieve higher capacity than the desktop prototype and reduce the overall cost of ownership of their hardware verification resources even as it helps to accelerate the verification cycle.
October 29, 2021 by Siemens Digital Industries Software
This paper outlines the multi-dimensional nature of this complexity and the costs and opportunities it generates. It also demonstrates that the key to designers meeting this challenge is the ability to attain system-level visibility: both during the semiconductor development cycle, and subsequently after embedded systems are deployed in the field.
August 30, 2021 by Siemens Digital Industries Software
Building blocks of modern embedded systems, including processors, SoCs, system DRAM, non-volatile memories, sensors, and connectivity modules, have varied power requirements. On one extreme, a system power management IC (PMIC) integrates all or almost all of the required power rails. On the other hand, individual power rails are implemented using discrete dc/dc and LDOs.
June 22, 2021 by ROHM Semiconductor
Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern generation (ATPG) and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected don’t consider the likelihood of one fault occurring compared to another.
June 17, 2021 by Siemens Digital Industries Software
This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP solution can be used with multiple types of hosts by supporting legacy PCIe 4.0, USB4, USB 3.x, and USB 2.0 connections.
May 12, 2021 by Synopsys
