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Category: All IP Cores (492)

OpenRISC 1000 Architecture 32/64-bit RISC/DSP

OpenRISC 1000 Architecture 32/64-bit RISC/DSP

Introduction The aim of the OpenRISC project is to create a free, open source computing platform available under the GNU (L)GPL license. Platform…

License : LGPL
Language : Verilog
Xilinx Spartan 6 PCI Express Card

Xilinx Spartan 6 PCI Express Card

Overview This article describe the PCI express card with Xilinx Spartan 6 that i have made. The download section contains test applications in…

License : LGPL
Language : VHDL
Digital Video Broadcasting (DVB-S2) LDPC Decoder

Digital Video Broadcasting (DVB-S2) LDPC Decoder

Introduction: From my thesis: Low-Density Parity Check (LDPC) coding is a form of error coding introduced by Gallager that can achieve performance…

License : LGPL
Language : Verilog
Verilog Fixed Point Math Library

Verilog Fixed Point Math Library

Synopsis Hey, this project has been downloaded many, *many* times it would seem. I'm glad you've found it useful. I would be interested in…

License : LGPL
Language : Verilog
2D FHT - Two Dimensional Fast Hartley Transform

2D FHT - Two Dimensional Fast Hartley Transform

RTL Verilog code to perform Two Dimensional Fast Hartley Transform (2D-FHT) for 8x8 points. Presented algorithm is FHT with decimation in frequency…

License : LGPL
Language : Verilog
Configurable CRC Core in Verilog

Configurable CRC Core in Verilog

n/a

License : LGPL
Language : Verilog
Configurable Parallel Scrambler Descrambler

Configurable Parallel Scrambler Descrambler

This is a behavioral module for parallel scrambler/descrambler. There are RTL scrambler modules available, the purpose of this project is to built…

License : LGPL
Language : VHDL
CORDIC Arctangent for IQ Signals

CORDIC Arctangent for IQ Signals

Streaming atan function based on CORDIC algorithm. [angle, modulus] = cordic([I, Q]) angle = atan(Q/I) modulus = sqrt(I^2+Q^2) angle in range…

License : LGPL
Language : Verilog
CRCAHB

CRCAHB

Arithmetic core originally created by: Cesar, Julio Fernandes, Felipe //// CRCAHB CORE BLOCK This file is part of the APB to I2C project…

License : LGPL
Language : Verilog
Double Precision Floating Point Unit IEEE-754 Compliant

Double Precision Floating Point Unit IEEE-754 Compliant

Features - The unit is designed to be synchronous to one global clock. All registers are updated on the rising edge of the clock. - All registers…

License : LGPL
Language : Verilog
FT816 Floating Point Accelerator

FT816 Floating Point Accelerator

07/06/2019 - Updated the square root core to allow restarting the calculation any time load is active. 06/14/2019 - Updates have been made to…

License : LGPL
Language : Verilog
Elliptic Curve Group Core

Elliptic Curve Group Core

The Elliptic Curve Group core is for computing the addition of two elements in the elliptic curve group, and the addition of $c$ identical elements…

License : LGPL
Language : Verilog
Fixed Point Arithmetic Modules Verilog

Fixed Point Arithmetic Modules Verilog

This project was started in order to create fixed point (Q format) arithmetic modules in verilog. What was created was a parameterized (specify…

License : LGPL
Language : Verilog
Efficient Floating Point Logarithm Unit for FPGAs

Efficient Floating Point Logarithm Unit for FPGAs

VHDL implementation of a fast space- and resource-efficient logarithm approximation unit for FPGAs. The unit is an implementation of the ICSILog…

License : LGPL
Language : VHDL
32-bit Fixed Point Square Root (Recursive Algorithm)

32-bit Fixed Point Square Root (Recursive Algorithm)

VHDL project for a Square Root Unit (SRU) for 32-bit fixed point data. The unit implements the Goldschmidt recursion algorithm. It is pipelined…

License : LGPL
Language : VHDL
Gaussian Noise Generator for FPGAs

Gaussian Noise Generator for FPGAs

The Gaussian Noise Generator core generates white Gaussian noise of standard normal distribution, which can be used to measure BER to extremely low…

License : LGPL
Language : Verilog
FPGA-based Median Filter Architecture

FPGA-based Median Filter Architecture

This implementation project proposes a practical implementation of a Median Filter architecture focused in low-cost FPGA devices. The architecture…

License : LGPL
Language : Verilog
Hardware Load Balancer for Multi-Stage Software Router

Hardware Load Balancer for Multi-Stage Software Router

n/a

License : LGPL
Language : VHDL
MESI Coherency InterSection Controller

MESI Coherency InterSection Controller

The MESI InterSection Controller (ISC) is a coherence system controller. It supports the MESI coherence protocol for a cache data consistency. It…

License : LGPL
Language : Verilog
Generic Galois LFSR in VHDL

Generic Galois LFSR in VHDL

This project implements the Galois Linear-feedback Shift Register (LFSR) in VHDL, and can be used for applications such as PRBS generation &…

License : LGPL
Language : VHDL