RadioHDL The purpose of RadioHDL is to speed up HDL development by providing a uniform and automated way of using tools and building code for…
This is synthesizeable radix 4 complex fft processor. Input data width and points are configurable. Output data width = Input data width + 2. Some…
Goal: Implement signed/unsigned 32/16 bit multiplier/divider using a finite state machine (and use it for a fun project) Background: I needed a…
This project implements a parameterized Reed Solomon decoder for use in OFDM wireless systems. Source code provided in C++ (trunk/cpp-source) and…
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A divider that calculates the quotient and remainder of a division operation in multiple clock cycles. The dividend, divisor, quotient and…
Sine and cosine table that can be synthesized. Pure VHDL, no other tools or silicon vendor macros. Pipeline delay can be selected from…
Before You Read This is a brief overview of the article about single-clock unsigned integer division algorithm. For comparison and estimation of…
Tiny Tate Bilinear Pairing core is for calculating Tate bilinear pairing. In fact it is a special type of Tate bilinear pairing called reduced…
The Tate Bilinear Pairing core is specially designed for running Tate bilinear pairing algorithm for hyperelliptic curve $y^2=x^3-x+1$ defined over…
The DLX processor is an academic processor described in in John L. Hennessy and David A. Patterson's Computer Architecture: A Quantitative…
Scalar risc cpu of my own architecture which features dynamic branch predictor (1-bit), single cycle load from l1 data cache, 4-way set-associative…
A custom instruction for approximation of the hyperbolic tangent function tanh(x) with a max. error of 0.1
This IP core provides resource efficient ternary adders, i.e., adders with three inputs performing s = x + y + z, for the Altera and Xilinx…
This core takes unsigned value as degrees(input) and gives the corresponding value in IEEE-754 double (output). This core can be easily configured…
kvcordic is a collection of files comprising an implementation of a universal CORDIC algorithm (rotation/vectoring direction,…
A versatile counter that can be defined as a binary, gray or LFSR counter. Usage include baudrate generator, address generator for FIFO and much…
The serial_divide_uu is a Verilog coded module that performs binary division. It is fully parameterized, and works in a serial fashion. The number…
EUS 100LX is an "open" system board conforming to the PC104 format (90,2mm x 95,9mm) designed for industrial control and data acquisition…
Target of this project is development FPGA and/or FPGA powered real time audio DSP applications. This is Free (like freedom) Hardware project, a…
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