Latest IC Design Industry White Papers

Critical Area Based Test Pattern Optimization

Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern generation (ATPG) and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected don’t consider the likelihood of one fault occurring compared to another.

Streaming Scan Network: A No-Compromise Approach to DFT

This white paper describes the basic components of the Tessent Streaming Scan Network (SSN), a technology designed to decouple core level and chip level DFT requirements. With SSN, DFT engineers can for the first time implement DFT using a true, effective bottom-up flow, not having to make trade-offs between implementation effort and manufacturing test cost.

Siemens, AMD, and Microsoft Collaborate on EDA In the Cloud

This white paper demonstrates how using a production 7nm design, AMD achieved a 2.5X speed up in physical verification cycle time.

New Approaches to Physical Verification Closure and Cloud Computing Come to the Rescue In the EUV Era

This white paper takes a look at how to replace inefficient, less precise verification processes with smarter, more accurate, faster, and more efficient functionality that can improve both the bottom line and product quality.

Mitigating Risks in Automotive IP and SoC with Safety Mechanisms

This white paper discusses faults and detectability by a safety mechanism, safety mechanism types and attributes, and how safety mechanism effectiveness is evaluated.

Flexible USB4-based Interface IP Solution for AI at the Edge

This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP solution can be used with multiple types of hosts by supporting legacy PCIe 4.0, USB4, USB 3.x, and USB 2.0 connections.

ON Semiconductor Gen 1 1200 V SiC MOSFETs & Modules: Characteristics and Driving Recommendations

This paper provides an overview of the key characteristics of ON Semiconductor Gen 1 1200 V SiC MOSFETs and how they can be influenced by the driving conditions. This resource also provides a guideline on the usage of the NCP51705 an isolated gate driver for SiC MOSFETs.

Leveraging 3D Layout to Optimize PCB System Designs

Some engineers believe that the 2D design is no longer sufficient for today’s complicated PCB layouts. Flex and rigid-flex designs, and an increasing need for collaboration with MCAD, require advanced 3D layout design capabilities to address today’s challenges fully.

Effective Return Loss: A New Metric for SerDes Channel or Package Characterization

A new metric for SerDes channel and package characterization is emerging. Effective Return Loss (ERL) is replacing the traditional frequency-domain Return Loss (RL) metric as a more effective means of characterizing SerDes channels.

Xilinx Healthcare Solutions Selector Guide

Identifying the right medical solutions for imaging, diagnostics, and clinical equipment is not easy. The growing needs of scalable healthcare platforms with heterogeneous multi-processing, I/O flexibility, hardware-based deterministic controls, and comprehensive solutions in healthcare artificial intelligence (AI), medical imaging, and safety & security add quite a bit of complexity to the decision process.

Accelerate Time to Market with Calibre nmLVS Recon Technology: A New Paradigm for Circuit Verification

One thing is clear — tapeouts are getting harder and taking longer. According to statistics from industry conference surveys, at least 50% of scheduled tapeouts slip each year.

Net Common Resistance Extraction is Crucial to Design Reliability

Accurately extracting and calculating the common resistance of interconnects within analog IC designs is fundamental for evaluating circuit reliability, particularly for noise and voltage drop analysis and ESD protection verification.

Improving Productivity With More Efficient LVS Debug

Layout versus schematic (LVS) verification is an essential and integral part of integrated circuit (IC) verification in a system-on-chip (SoC) design cycle, but with today’s highly dense and hierarchical layouts, increasing circuit complexity, and intricate foundry rules, running LVS can be a time-consuming and resource-intensive endeavor.

How to Successfully Calibrate an Open-Loop DAC Signal Chain

The monitoring and testing of a DAC signal chain are critical considerations for open-loop applications. Errors in a DAC signal chain, including DAC intrinsic errors that vary depending on the system, can significantly disrupt the customer design-in experience.

How Software Configurable Hardware Helps Flexibility in Industrial I/O Modules

Whether used for a process control installation or an industrial automation system, an I/O module (or a field junction box) poses a host of unique challenges in a product's life cycle. Product management, for example, faces key decisions on how many channels and which combinations will be necessary for each product.

Power-Up Phase Determinism Using Multichip Synchronization Features in Integrated Wideband DACs and ADCs

μModule Data Acquisition Solution Eases Engineering Challenges for a Diverse Set of Precision Applications

The electronic industry’s dynamics are rapidly evolving, and there is less time to build and prototype analog circuits to verify their functionality as the control of research and development (R&D) budgets and time to market (TTM) have become more challenging.

Teleoperation: Remote Operation of Connected & Autonomous Vehicles