Explore EMI challenges associated with migrating a design from Si to SiC, test tools and test methodology, along with mitigation and optimization techniques.
Explore EMI challenges associated with migrating a design from Si to SiC, test tools and test methodology, along with mitigation and optimization techniques.
Explore the advantages of the next generation in IGBT technology and how this benefits industrial and automotive applications.
Explore the advantages of the next generation in IGBT technology and how this benefits industrial and automotive applications.
Heterogeneous IC integration is an inflection point that’s not only bringing new architectures into the market but also…
Heterogeneous IC integration is an inflection point that’s not only bringing new architectures into the market but also disrupting the engineering process. How Siemens 3D IC helps you engineer a smarter future faster.
Capturing the intended system-level connectivity in a multi-substrate 3D IC assembly can be a challenge. This is…
Capturing the intended system-level connectivity in a multi-substrate 3D IC assembly can be a challenge. This is especially true when each substrate is built using a different methodology, team, and/or format.
Ensure correct-by-construction filler cell insertion in less time, while using standard industry interfaces that…
Ensure correct-by-construction filler cell insertion in less time, while using standard industry interfaces that seamlessly integrate with both the P&R and physical verification tools.
Mitigating Cross-Fabric Thermal and Stress Barriers to 3D-ICs
Mitigating Cross-Fabric Thermal and Stress Barriers to 3D-ICs
NEW tech paper - automated scalable power integrity analysis tool for analog designs
NEW tech paper - automated scalable power integrity analysis tool for analog designs
As part of a growing suite of innovative early-stage design verification technologies, the Calibre nmLVS Recon tool…
As part of a growing suite of innovative early-stage design verification technologies, the Calibre nmLVS Recon tool enables design teams to rapidly examine dirty and immature designs to find and fix high-impact circuit errors earlier and faster, leading to an overall reduction in tapeout schedules and time to market.
Several factors are converging and driving the chiplet design revolution. This paper explores these factors and outlines…
Several factors are converging and driving the chiplet design revolution. This paper explores these factors and outlines five key workflows that address and manage the associated, new challenges. The paper recommends workflow adoption focus areas that provide immediate heterogeneous integration capability benefits while establishing a managed methodology adoption and migration process that minimizes disruption, risk, and cost. This will bring heterogeneous integration-based chiplet design within reach of the mainstream instead of being accessible only to the mega iDMs and fabless semiconductor companies.
In this white paper, the Siemens EDA tool provides a modular, scalable desktop prototyping platform for early software…
In this white paper, the Siemens EDA tool provides a modular, scalable desktop prototyping platform for early software development.
Eliminate frustrating DFM delays from your next HDI board build.
Eliminate frustrating DFM delays from your next HDI board build.
Characterize and minimize complexity for PCB fabrication and assembly.
Characterize and minimize complexity for PCB fabrication and assembly.
Learn four EDA secrets to mastering mmWave communications circuit design and how to streamline your design workflow to…
Learn four EDA secrets to mastering mmWave communications circuit design and how to streamline your design workflow to achieve first-pass success.
In this case study, learn how the Aprisa software was able to implement a powerful and flexible RTL-GDSII design flow…
In this case study, learn how the Aprisa software was able to implement a powerful and flexible RTL-GDSII design flow that was easy to use, fast, technology ready, and with excellent correlation with sign-off to reduce iterations.
Learn from this panel of experts addressing artificial intelligence's impact on the on the semiconductor industry,…
Learn from this panel of experts addressing artificial intelligence's impact on the on the semiconductor industry, specifically, chip design verification.
Learn how to create a new verification flow that combines emulation and X STEP, a platform that can generate, capture,…
Learn how to create a new verification flow that combines emulation and X STEP, a platform that can generate, capture, and analyze bit-accurate fronthaul traffic.
This paper describes how a PreScan, Veloce, and AMEsim tool flow provides the thoroughness of verification to get new…
This paper describes how a PreScan, Veloce, and AMEsim tool flow provides the thoroughness of verification to get new cars on the road quickly, efficiently, and safely.
Explore the advantages and benefits of Veloce VirtuaLAB emulation, backed up by three test cases.
Explore the advantages and benefits of Veloce VirtuaLAB emulation, backed up by three test cases.
This eBook covers an approach that allows for the design of a myriad of interface standards without increasing design…
This eBook covers an approach that allows for the design of a myriad of interface standards without increasing design and verification time.
This white paper from Siemens Digital Industries Software demonstrates how running Calibre PERC verification flows on…
This white paper from Siemens Digital Industries Software demonstrates how running Calibre PERC verification flows on cloud hardware resources to satisfy peak demand usage can increase productivity and expedite turnaround times.
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